PPKE ITK PhD and MPhil Thesis Classes

4.7 Results 105
Table 4.1: Comparison of a modified Falcon PE and the proposed GAPU in
terms of device utilization and achievable clock frequency. The configuration of
state width is 18 bit. (The asterisk denotes that in Virtex-5 FPGAs, the slices
differently organized, and they contain twice as much LUTs and FlipFlops as the
previous generations).
Device
utilization
and speed
Num. of
occupied slices
Num. of
BRAMs
Num. of
MULT18×18s
Core
frequency [MHz]
MicroBlaze
GAPU
(@18 bit)
Falcon PE
(@18 bit)
Available on
XC2V3000
Available on
XC6VSX475T
1780 452 14 336 74400*
18 5 96 2128
0 9 96 2016
100 133 133 600 (210)
the currently available largest DSP-specialized Virtex-6 SX475T FPGA has to
be used where the GAPU occupies only a minimal additional area (about 2.4%
of slices and only 1% of BRAMs). With the use of this device, 160 Falcon PE
cores can be implemented in an array, as well. The other large-sized Virtex-
II Pro or Virtex4 FX or Virtex5 FX platform FPGAs provide embedded IBM
PowerPC405 hard processor core(s) at a higher speed, which may be a good
alternative to implement GAPU in further development. There are only rumors
about the newest 7th series Xilinx FPGAs, which will embed ARM processor
core.
4.7 Results
Considering consecutive analog operations (e.g., the black and white skeletonization
above) on a 64 × 64 image with 18-bit state-, constant- and 9-bit templateprecision,
the Falcon PE cores perform 10 iterations within 0.307 ms. Without the
proposed GAPU extension, due to the slow communication via the parallel port
(downloading / uploading the sequence of instructions, templates, and results),
the data transfer requires approximately 204.8 ms, while the full computing time