PPKE ITK PhD and MPhil Thesis Classes

List of Tables
2.1 Comparison of different CNN implementations: 2GHz CORE 2
DUO processor, Emulated Digital CNN running on Cell processors
and on Virtex 5 SX240T FPGA, and Q-EYE with analog VLSI chip 49
2.2 The initial state, and the results of the simulation after a couple
of iteration steps. Where the x- and y-axis models 1024km width
ocean (1 untit is equal to 2.048km). . . . . . . . . . . . . . . . . . 52
2.3 Comparison of different CNN ocean model implementations: 2GHz
CORE 2 DUO processor, Emulated Digital CNN running on Cell
processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.4 Comparison of different hardware implementations . . . . . . . . . 68
4.1 Comparison of a modified Falcon PE and the proposed GAPU
in terms of device utilization and achievable clock frequency. The
configuration of state width is 18 bit. (The asterisk denotes that in
Virtex-5 FPGAs, the slices differently organized, and they contain
twice as much LUTs and FlipFlops as the previous generations). . 105
4.2 Comparison of the different host interfaces. . . . . . . . . . . . . . 106
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