PPKE ITK PhD and MPhil Thesis Classes

10 1. INTRODUCTION
accelerator can be implemented either on multi-processor VLSI ASIC digital emulators
(e.g CASTLE) [26], on DSP-, SPE-, and GPU-based hardware accelerator
boards (e.g. CNN-HAC [27], Cell Broadband Engine Architecture [28], Nvidia
Cuda [29], respectively), on FPGA-based reconfigurable computing architectures
(e.g. FALCON [30]), as well. Generally, they speed up the software simulators,
to get higher performance, but they are slower than the analog/mixed-signal
CNN-UM implementations.
A special Hardware Accelerator Board (HAB) was developed for simulating
up to one-million-pixel arrays (with on-board memory) with four DSP (16 bit
fixed point) chips. In fact, in a digital HAB, each DSP calculates the dynamics
of a partition of the whole CNN array. Since for the calculation of the CNN
dynamics a major part of DSP capability is not used, special purpose chips have
been developed.
The first emulated-digital, custom ASIC VLSI CNN-UM processor – called
CASTLE.v1 – was developed in MTA-SZTAKI in Analogical and Neural Computing
Laboratory between 1998 and 2001 for processing binary images [26], [31].
By using full-custom VLSI design methodology, this specialized systolic CNN
array architecture greatly reduced the area requirements of the processor and
makes it possible to implement multiple processing elements (with distributed
ALUs) on the same silicon die. The second version of the CASTLE processor
was elaborated with variable computing precision (1-bit ’logical’ and 6/12-bit
’bitvector’ processing modes), its structure can be expanded into an array of
CASTLE processors. Moreover, it is capable of processing 240×320-sized images
or videos at 25fps in real-time with low power dissipation (in mW range), as
well. Emulated-digital approach can also benefit from scaling-down by using new
manufacturing technologies to implement smaller and faster circuits with reduced
power dissipation.
Several fundamental attributes of the Falcon architecture [30] are based on
CASTLE emulated-digital CNN-UM array processor architecture. However, the
most important features which were greatly improved in this FPGA-based implementation
are the flexibility of programming, the scalable accuracy of CNN
computations, and configurable template size. Therefore, the majority of these