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4. IMPLEMENTING A GLOBAL ANALOGIC PROGRAMMING UNIT 90 FOR EMULATED DIGITAL CNN PROCESSORS ON FPGA StateIn ConstIn TmpselIn LeftOut LeftIn LeftInNew Mixer unit Memory unit Template memory RightOut RightOutNew RightIn Control unit Enable DataValidIn DataValidOut Arithmetic unit StateOut ConstOut TmpselOut Figure 4.1: The structure of the general Falcon processor element is optimized for GAPU integration. Main building blocks and signals with an additional low-level Control unit are depicted. The integrated Control logic has three different control signals: the Enable allows the operation of the Falcon processor element (FPE) for one clock cycle, the DataValidIn denotes that valid input data arrived, while DataValidOut indicates the first computed result. Depending on the template size, several rows from the given layer should be stored in the Memory unit. It must be supplied with input data from the main memory (RAM) of the proposed CNN-UM implementation. The arithmetic unit is modified and optimized for GAPU. Which can be built up from (2r + 1) × (2r + 1) multipliers instead of r dedicated elements. This means that it is capable of computing the new state value within one clock cycle, supposing nearest neighborhood (r=1) templates and a single-layer structure. The hardware complexity of the application increases quadratically as the number of layers are
4.3 Implementation 91 increased, so for multi-layer structures the arithmetic core must perform r 2 times more computations than in the single-layer case, and the templates may be treated as r × r pieces of single-layer templates. The input picture is partitioned among the physical FPEs: each column of the processors works on vertical stripe of the image, while each row executes one iteration step in the discretized time. The inter-processor communication is solved on processor level. However, certain timing and control signals must be supplied to the first processor row in order to indicate the processing elements when the first input data are available. On the other hand, the input pipeline gets the value of the last pixel in a row, as pixel values are stored continuously in the RAM. These signals ensure the duplication of the first and last rows of pixels satisfying the Neumann-type (zero-flux) boundary condition. One possible problem might be that prototyping boards usually have different memory-bus width than the Falcon array has. For this reason an Input and Output Interface are necessary to be implemented between the on-board RAM memory and the Falcon array (in Figure 4.2). The Falcon interface multiplexes and transforms multiple words of data (width of the data bus) into a w wide data word, according to the following equation: w = n × (w s + w c + w ts ) , (4.3) where n means columns of processors, each one works with w s bits of state, w c bits of constant, and w ts bits of template width. This might be a bottle-neck in speed, but it can be eliminated by the careful selection of the number of processor elements. An additional Arbiter unit provides the communication with necessary bus control and gating logic. 4.3 Implementation 4.3.1 Objectives Since the Falcon processor is only capable of computing the result of one iteration step on the picture stored in the on-board RAM, it should be extended with an additional high-level control unit, called GAPU, when more iteration steps are
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An Optimal Mapping of Numerical Sim
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Acknowledgements It is not so hard
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Contents 1 Introduction 1 1.1 Cellu
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CONTENTS iii 4.3.3 Operating Steps
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vi LIST OF FIGURES 2.4 Performance
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List of Tables 2.1 Comparison of di
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xii LIST OF ABBREVIATIONS FPE Falco
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Chapter 1 Introduction Due to the r
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3 can be represented in arbitrary t
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1.1 Cellular Neural/Nonlinear Netwo
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1.2 Cellular Neural/Nonlinear Netwo
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1.3 CNN-UM Implementations 9 the Lo
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1.3 CNN-UM Implementations 11 modif
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1.4 Field Programmable Gate Arrays
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1.5 IBM Cell Broadband Engine Archi
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Chapter 2 Mapping the Numerical Sim
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2.1 Introduction 37 18 Load instruc
Page 59 and 60: 2.1 Introduction 39 Instruction his
Page 61 and 62: 2.1 Introduction 41 2E+07 1E+07 9E+
Page 63 and 64: 2.1 Introduction 43 Main memory 8 t
Page 65 and 66: 2.1 Introduction 45 6 4.5 3 Speedup
Page 67 and 68: 2.1 Introduction 47 2.50E+07 1.88E+
Page 69 and 70: 2.2 Ocean model and its implementat
Page 71 and 72: 2.2 Ocean model and its implementat
Page 73 and 74: 2.3 Computational Fluid Flow Simula
Page 89 and 90: Chapter 3 Investigating the Precisi
Page 91 and 92: 3.2 Numerical Solutions of the PDEs
Page 93 and 94: 3.3 Testing Methodology 73 In fixed
Page 95 and 96: 3.4 Properties of the Arithmetic Un
Page 97 and 98: 3.4 Properties of the Arithmetic Un
Page 99 and 100: 3.5 Results 79 in the L2 cache of t
Page 101 and 102: 3.5 Results 81 1E-02 1E-03 Error 1E
Page 103 and 104: 3.5 Results 83 arithmetic unit requ
Page 105: 3.6 Conclusion 85 point and the 40
Page 108 and 109: 4. IMPLEMENTING A GLOBAL ANALOGIC P
Page 130 and 131: 110 5. SUMMARY OF NEW SCIENTIFIC RE
Page 141 and 142: References The author’s journal p
Page 143 and 144: 5.2 Application of the results 123
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PPKE ITK PhD and MPhil Thesis Classes

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