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3. INVESTIGATING THE PRECISION OF PDE SOLVER
ARCHITECTURES ON FPGAS
in Figure (3.1) in the floating point first order discretization case. The slope of
the error curves in different precision in fixed point first order and second order
discretization case are similar to the floating point first order case in different
grid resolution. This increasing should be done until the required accuracy of the
solution is reached. There are two cases, when the selected arithmetic precision
is not satisfactory:
• With the increase of the grid resolution may results, that the truncation
and roundoff error overcomes the method error before the required accuracy
is reached. In this case a higher precision arithmetic should be chosen, and
the iterative grid refining should be restarted.
• If the required accuracy of the solution is reached before a grid resolution
(truncation and roundoff error domination), then a lower precision arithmetic
unit can be selected in order to use a smaller architecture.
To find the proper arithmetic precision for the required accuracy, the minimum
point of the curve should be determined with the pre defined grid resolution
(e.g.: the 38 bit width with 10 4 grid resolution in Figure (3.1)) where the larger
arithmetic precision does not result in higher accuracy. With this method the
minimal grid resolution can be determined for an expected accuracy with the
investigation of the roundoff and truncation error in different arithmetic precision.
After the first couple of floating-point simulations using moderate grid size it
turned out, that the complete testing of even the lowest 29 bit precision case will
take more than 200 hours. That is why we decided to make an arithmetic unit
on FPGA.
3.4 Properties of the Arithmetic Units on FPGA
The purpose was not to gain the highest speed with an acceleration board, but
to investigate the precision of a computation, there for a familiar development
board is used. The architecture was developed on a Xilinx XC2V6000 FPGA
[37], which takes place on an Alpha Data [66] board. It contains 33,792 slices,
144 18 × 18 bit multipliers and 144 18Kb BlockRAMs. It is not the latest FPGA,
but it represents well todays low cost, low power FPGA.