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20 1. INTRODUCTION 1.4.3 Dedicated elements, heterogenous structure In advanced FPGAs specialized blocks were also available. These blocks (e.g.: embedded memory, arithmetic unit, or embedded microprocessor) are implemented because they are commonly used elements, therefore the specialized blocks are using less general resources from the FPGA. The result is a highly heterogenous structure. The memory is a basic building block of the digital system. Flip-flops can be used as a memory, but it will not be efficient in case of storing large amount of data. Firstly in case of Xilinx XC4000 FPGA were the LUTs enough flexible to use it as an asynchronous 16×1 bit RAM. Later it evolved to use as a dual-ported RAM or as a shift register. These clusters can be arranged in a flexible way to implement larger bit-width or deeper memory. E.g.: In case of a 4Kb on-chip RAM on Xilinx Virtex FPGA can be defined in the following hierarchical way: 4096 × 1, 2048 × 2, 1024 × 4, 512 × 8, 256 × 16. Among the adders, which builds up from logical elements, in FPGA we can use embedded multipliers, or Digital Signal Processing (DSP) blocks like separate, dedicated resources. The DSP block can make addition, subtraction, multiplication or multiply-accumulate (MAC) operation. The solving of a MAC operation in one clock cycle can be useful for finite-impulse response (FIR) filtering (which occurs in many DSP applications). The FPGA manufacturers are integrating complete dedicated microprocessors into their devices in order to implement low bandwidth and/or complex controlling functions. With this capability (nearly) fully embedded systems can be implemented on the FPGA. The embedded processor can be found on Xilinx Virtex-II Pro, on Xilinx Virtex-4 and on Xilinx Virtex-5 FPGA. The Xilinx integrates dedicated hard processor cores (e.g.: IBM PowerPC405) into their devices (see Figure 1.11). These embedded processors are connected with on-chip SRAMs. That means without the configuration of the FPGA it can not make any useful work.
1.4 Field Programmable Gate Arrays 21 Figure 1.11: IBM PowerPC405 processor integration on Xilinx FPGA
Page 1: An Optimal Mapping of Numerical Sim
Page 5 and 6: Acknowledgements It is not so hard
Page 7 and 8: Contents 1 Introduction 1 1.1 Cellu
Page 9: CONTENTS iii 4.3.3 Operating Steps
Page 12 and 13: vi LIST OF FIGURES 2.4 Performance
Page 15: List of Tables 2.1 Comparison of di
Page 18 and 19: xii LIST OF ABBREVIATIONS FPE Falco
Page 21 and 22: Chapter 1 Introduction Due to the r
Page 23 and 24: 3 can be represented in arbitrary t
Page 25 and 26: 1.1 Cellular Neural/Nonlinear Netwo
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3.2 Numerical Solutions of the PDEs
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3.3 Testing Methodology 73 In fixed
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3.4 Properties of the Arithmetic Un
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3.4 Properties of the Arithmetic Un
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3.5 Results 79 in the L2 cache of t
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3.5 Results 81 1E-02 1E-03 Error 1E
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3.5 Results 83 arithmetic unit requ
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3.6 Conclusion 85 point and the 40
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4. IMPLEMENTING A GLOBAL ANALOGIC P
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References The author’s journal p
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5.2 Application of the results 123
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