PPKE ITK PhD and MPhil Thesis Classes

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4. IMPLEMENTING A GLOBAL ANALOGIC PROGRAMMING UNIT 104 FOR EMULATED DIGITAL CNN PROCESSORS ON FPGA 20 15 10 Utilization 5 0 2 4 6 8 10 12 14 16 18 24 32 BRAM (FALCON) BRAM (GAPU) State width (bit) Figure 4.7: Number of required BlockRAMs in different precision
4.7 Results 105 Table 4.1: Comparison of a modified Falcon PE and the proposed GAPU in terms of device utilization and achievable clock frequency. The configuration of state width is 18 bit. (The asterisk denotes that in Virtex-5 FPGAs, the slices differently organized, and they contain twice as much LUTs and FlipFlops as the previous generations). Device utilization and speed Num. of occupied slices Num. of BRAMs Num. of MULT18×18s Core frequency [MHz] MicroBlaze GAPU (@18 bit) Falcon PE (@18 bit) Available on XC2V3000 Available on XC6VSX475T 1780 452 14 336 74400* 18 5 96 2128 0 9 96 2016 100 133 133 600 (210) the currently available largest DSP-specialized Virtex-6 SX475T FPGA has to be used where the GAPU occupies only a minimal additional area (about 2.4% of slices and only 1% of BRAMs). With the use of this device, 160 Falcon PE cores can be implemented in an array, as well. The other large-sized Virtex- II Pro or Virtex4 FX or Virtex5 FX platform FPGAs provide embedded IBM PowerPC405 hard processor core(s) at a higher speed, which may be a good alternative to implement GAPU in further development. There are only rumors about the newest 7th series Xilinx FPGAs, which will embed ARM processor core. 4.7 Results Considering consecutive analog operations (e.g., the black and white skeletonization above) on a 64 × 64 image with 18-bit state-, constant- and 9-bit templateprecision, the Falcon PE cores perform 10 iterations within 0.307 ms. Without the proposed GAPU extension, due to the slow communication via the parallel port (downloading / uploading the sequence of instructions, templates, and results), the data transfer requires approximately 204.8 ms, while the full computing time
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An Optimal Mapping of Numerical Sim
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Acknowledgements It is not so hard
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Contents 1 Introduction 1 1.1 Cellu
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CONTENTS iii 4.3.3 Operating Steps
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vi LIST OF FIGURES 2.4 Performance
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List of Tables 2.1 Comparison of di
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xii LIST OF ABBREVIATIONS FPE Falco
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Chapter 1 Introduction Due to the r
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3 can be represented in arbitrary t
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1.1 Cellular Neural/Nonlinear Netwo
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1.2 Cellular Neural/Nonlinear Netwo
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1.3 CNN-UM Implementations 9 the Lo
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1.3 CNN-UM Implementations 11 modif
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1.4 Field Programmable Gate Arrays
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1.5 IBM Cell Broadband Engine Archi
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Chapter 2 Mapping the Numerical Sim
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2.1 Introduction 37 18 Load instruc
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2.1 Introduction 39 Instruction his
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2.1 Introduction 41 2E+07 1E+07 9E+
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2.1 Introduction 43 Main memory 8 t
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2.1 Introduction 45 6 4.5 3 Speedup
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2.1 Introduction 47 2.50E+07 1.88E+
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2.2 Ocean model and its implementat
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2.2 Ocean model and its implementat
Page 73 and 74: 2.3 Computational Fluid Flow Simula
Page 89 and 90: Chapter 3 Investigating the Precisi
Page 91 and 92: 3.2 Numerical Solutions of the PDEs
Page 93 and 94: 3.3 Testing Methodology 73 In fixed
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Page 99 and 100: 3.5 Results 79 in the L2 cache of t
Page 101 and 102: 3.5 Results 81 1E-02 1E-03 Error 1E
Page 103 and 104: 3.5 Results 83 arithmetic unit requ
Page 105: 3.6 Conclusion 85 point and the 40
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Page 130 and 131: 110 5. SUMMARY OF NEW SCIENTIFIC RE
Page 141 and 142: References The author’s journal p
Page 143 and 144: 5.2 Application of the results 123
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PPKE ITK PhD and MPhil Thesis Classes

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