PPKE ITK PhD and MPhil Thesis Classes

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4. IMPLEMENTING A GLOBAL ANALOGIC PROGRAMMING UNIT 100 FOR EMULATED DIGITAL CNN PROCESSORS ON FPGA signal processing coming from PAL or NTSC video cameras, as well. Several parts of these predefined interfaces are provided from the Platform Abstraction Layer (PAL) API of Celoxica [32]. 4.5 An Example The example shows the functionality of GAPU, by using a skeletonization algorithm where a lot of template replacements should be performed in each iteration step. This may increase significantly the communication (download/upload) time between the host PC and FPGA, and this will be the great bottleneck when calculating the full processing time. Consequently, if we apply the embedded GAPU, it will reduce the communication time, and it provides a more efficient utilization of the Falcon processor. The analogic algorithm in this example finds the skeleton of a black-and-white object. The 8 different templates should be applied circularly, always feeding the output result back to the input before using the next template. The templates of the algorithm are as follows (using the up-to-date Cellular Wave Computing Library [76]):
4.5 An Example 101 Input 1 st iteration 5 th iteration 10 th iteration Figure 4.5: Results after some given iteration steps of the black and white skeletonization. SKELBW1: ⎡ ⎤ SKELBW2: ⎡ ⎤ 1 1 0 2 2 2 B 1 = ⎣ 1 5 −1 ⎦ z 1 = −1 B 2 = ⎣ 0 9 0 ⎦ z 2 = −2 0 −1 0 −1 −2 −1 SKELBW3: ⎡ ⎤ SKELBW4: ⎡ ⎤ 0 1 1 −1 0 2 B 3 = ⎣ −1 5 1 ⎦ z 3 = −1 B 4 = ⎣ −2 9 2 ⎦ z 4 = −2 0 −1 0 −1 0 2 SKELBW5: ⎡ B 5 = ⎣ SKELBW7: ⎡ B 7 = ⎣ 0 −1 0 −1 5 1 0 1 1 0 −1 0 1 5 −1 1 1 0 ⎤ SKELBW6: ⎡ ⎦ z 5 = −1 B 6 = ⎣ ⎤ FEEDBACK ⎡ TEMPLATES: ⎤ 0 0 0 A n = ⎣ 0 1 0 0 0 0 SKELBW8: ⎡ ⎦ z 7 = −1 B 8 = ⎣ ⎦ (n = 1...8) −1 −2 −1 0 9 0 2 2 2 2 0 −1 2 9 −2 2 0 −1 ⎤ ⎦ z 6 = −2 ⎤ ⎦ z 8 = −2 where B i denotes the control templates, while A n denotes the feedback matrix (the same for all directions). The algorithm runs on the SKELBWI.bmp and the size of the image is 128 × 128. The results of the algorithm are plotted below, in Figure 4.5. The above analogic CNN algorithm had been implemented on the experimental system, based on Virtex-II FPGA with high-level software API (collection of functions), which makes it possible to control the communication of the GAPU
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An Optimal Mapping of Numerical Sim
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Acknowledgements It is not so hard
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Contents 1 Introduction 1 1.1 Cellu
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CONTENTS iii 4.3.3 Operating Steps
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vi LIST OF FIGURES 2.4 Performance
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List of Tables 2.1 Comparison of di
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xii LIST OF ABBREVIATIONS FPE Falco
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Chapter 1 Introduction Due to the r
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3 can be represented in arbitrary t
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1.1 Cellular Neural/Nonlinear Netwo
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1.2 Cellular Neural/Nonlinear Netwo
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1.3 CNN-UM Implementations 9 the Lo
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1.3 CNN-UM Implementations 11 modif
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1.4 Field Programmable Gate Arrays
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1.5 IBM Cell Broadband Engine Archi
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Chapter 2 Mapping the Numerical Sim
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2.1 Introduction 37 18 Load instruc
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2.1 Introduction 39 Instruction his
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2.1 Introduction 41 2E+07 1E+07 9E+
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2.1 Introduction 43 Main memory 8 t
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2.1 Introduction 45 6 4.5 3 Speedup
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2.1 Introduction 47 2.50E+07 1.88E+
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Page 141 and 142: References The author’s journal p
Page 143 and 144: 5.2 Application of the results 123
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PPKE ITK PhD and MPhil Thesis Classes

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