PPKE ITK PhD and MPhil Thesis Classes

More documents

Recommendations

Info

4. IMPLEMENTING A GLOBAL ANALOGIC PROGRAMMING UNIT 98 FOR EMULATED DIGITAL CNN PROCESSORS ON FPGA 7. If the computation reaches the last row of the picture, the number of iterations should be decreased by 1, and the AddrIn and AddrOut registers should be deleted. The above steps will be iteratively performed, until the given number of iteration step is obtained. At this point the analog operation will be accomplished. In the other case if we want to perform a logical or an arithmetic operation on an arbitrary sized binary picture, in the Command register a flag of the given instruction should be set, enabling the selected operation of the Vector processor element. The function of registers is similar to the above analog operation, but in case of logical processing, it is not necessary to use the iteration counter registers, because only one iteration should be performed. These low-level operations may be hidden by a higher level software API, which makes it possible to control the communication between the MicroBlaze core and the Falcon or Vector processor cores. In order to provide suitable user interface, in addition, these functions simplify the download of input pictures and template values onto the processor elements, starting the CNN computation with given templates together with an arbitrary number of iterations, and finally uploading, furthermore, displaying the computed results. 4.4 The real image processing system In the real image processing system, based on the RC203 FPGA development board [75], several interfaces are implemented to handle the memory, parallel port, camera input and video output parts, as shown in Figure 4.4. Storing the partial results of calculation, the processors can access the onboard memory through the implemented ZBT interface. A Memory Arbitration unit decides on the component that can be used by the memory. The FIFO elements need to match the bit-width differences between the ZBT memory and other functional elements. The Parallel Port interface is applied to attach the system to the host PC for configuring (downloading / uploading) the processor. The VGA interface is necessary to connect the monitor which can display the computed results, while the video input of the system supports on-line video
4.4 The real image processing system 99 ZBT SRAM 0 ZBT SRAM 1 ZBT Interface Memory Arbitration Unit FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO Paralel Port Interface Falcon processor Vector processor VGA Interface Camera Interface Celoxica PAL GAPU (MicroBlaze) Celoxica PAL Celoxica PAL Paralel Port to Host PC Video Output Video Input Figure 4.4: Block diagram of the experimental system. The embedded GAPU is connected with Falcon and Vector processing elements on FPGA.
Page 1:
An Optimal Mapping of Numerical Sim
Page 5 and 6:
Acknowledgements It is not so hard
Page 7 and 8:
Contents 1 Introduction 1 1.1 Cellu
Page 9:
CONTENTS iii 4.3.3 Operating Steps
Page 12 and 13:
vi LIST OF FIGURES 2.4 Performance
Page 15:
List of Tables 2.1 Comparison of di
Page 18 and 19:
xii LIST OF ABBREVIATIONS FPE Falco
Page 21 and 22:
Chapter 1 Introduction Due to the r
Page 23 and 24:
3 can be represented in arbitrary t
Page 25 and 26:
1.1 Cellular Neural/Nonlinear Netwo
Page 27 and 28:
1.2 Cellular Neural/Nonlinear Netwo
Page 29 and 30:
1.3 CNN-UM Implementations 9 the Lo
Page 31 and 32:
1.3 CNN-UM Implementations 11 modif
Page 33 and 34:
1.4 Field Programmable Gate Arrays
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
Page 41 and 42:
Page 43 and 44:
Page 45 and 46:
Page 47 and 48:
1.5 IBM Cell Broadband Engine Archi
Page 49 and 50:
Page 51 and 52:
Page 53 and 54:
Page 55 and 56:
Chapter 2 Mapping the Numerical Sim
Page 57 and 58:
2.1 Introduction 37 18 Load instruc
Page 59 and 60:
2.1 Introduction 39 Instruction his
Page 61 and 62:
2.1 Introduction 41 2E+07 1E+07 9E+
Page 63 and 64:
2.1 Introduction 43 Main memory 8 t
Page 65 and 66:
2.1 Introduction 45 6 4.5 3 Speedup
Page 67 and 68: 2.1 Introduction 47 2.50E+07 1.88E+
Page 69 and 70: 2.2 Ocean model and its implementat
Page 71 and 72: 2.2 Ocean model and its implementat
Page 73 and 74: 2.3 Computational Fluid Flow Simula
Page 89 and 90: Chapter 3 Investigating the Precisi
Page 91 and 92: 3.2 Numerical Solutions of the PDEs
Page 93 and 94: 3.3 Testing Methodology 73 In fixed
Page 95 and 96: 3.4 Properties of the Arithmetic Un
Page 97 and 98: 3.4 Properties of the Arithmetic Un
Page 99 and 100: 3.5 Results 79 in the L2 cache of t
Page 101 and 102: 3.5 Results 81 1E-02 1E-03 Error 1E
Page 103 and 104: 3.5 Results 83 arithmetic unit requ
Page 105: 3.6 Conclusion 85 point and the 40
Page 108 and 109: 4. IMPLEMENTING A GLOBAL ANALOGIC P
Page 130 and 131: 110 5. SUMMARY OF NEW SCIENTIFIC RE
Page 141 and 142: References The author’s journal p
Page 143 and 144: 5.2 Application of the results 123
show all

PPKE ITK PhD and MPhil Thesis Classes

Create successful ePaper yourself

Delete template?

Save as template?