PPKE ITK PhD and MPhil Thesis Classes

More documents

Recommendations

Info

78 3. INVESTIGATING THE PRECISION OF PDE SOLVER ARCHITECTURES ON FPGAS Figure 3.4: Structure of the system with the accelerator unit 13!000 Number of slices 9!750 6!500 3!250 0 29bit 31bit 33bit 35bit 37bit 39bit 1st order 2nd order Figure 3.5: Number of slices of the Accelerator Unit in different precisions
3.5 Results 79 in the L2 cache of the processor comfortably. However the architecture implemented on the FPGA was not optimized for speed and runs only on 100MHz, its performance is comparable or in some cases slightly higher than a 3GHz Intel Core 2 Duo microprocessor. 3.5 Results The L ∞ norm of the error in case of different grid resolution and different fixedpoint and floating-point precisions are compared in Figure (3.6) – (3.8). As the resolution is increased, the accuracy of the solution can be improved. Finer grid resolution requires smaller time-step, according to the CFL condition, which results in more operations. After a certain number of steps the round-off error of the computation will be comparable or larger than the truncation error of the numerical method. Therefore the step size can not be decreased to zero in a given precision. The precision of the arithmetic units should be increased when the grid is refined. The arithmetic unit in the 2nd order case (see Figure 3.7) is twice as large as in 1st order arithmetic unit, additionally the step-size should be halved therefore four times more computation is required. The slope of the error is higher as shown in Figure 3.9, therefore computation on a coarser grid results in higher accuracy. The L ∞ norm of fix-point and floating point solutions with the same mantissa width are compared in Figure 3.9. Because we use 11 bit for the exponent in floating-point numbers the 40 bit floating point number compared to the 29 bit fix-point number. As it can be seen, the floating-point computation results in more accurate solution than the fix-point. But just adding four bits to the 29bit fixed-point number and using 33bit fixed-point number the L ∞ norm of the error is comparable to the error of the 40bit floating point computations. In addition 7 bits are saved, which results in lower memory bandwidth and has a reduced area requirement. The fixed-point arithmetic unit requires 22 multipliers while the floating-point arithmetic unit requires only 16 multipliers, the number of required slices is far more less in the fixed-point case. While the 34 bit fixed-point
Page 1:
An Optimal Mapping of Numerical Sim
Page 5 and 6:
Acknowledgements It is not so hard
Page 7 and 8:
Contents 1 Introduction 1 1.1 Cellu
Page 9:
CONTENTS iii 4.3.3 Operating Steps
Page 12 and 13:
vi LIST OF FIGURES 2.4 Performance
Page 15:
List of Tables 2.1 Comparison of di
Page 18 and 19:
xii LIST OF ABBREVIATIONS FPE Falco
Page 21 and 22:
Chapter 1 Introduction Due to the r
Page 23 and 24:
3 can be represented in arbitrary t
Page 25 and 26:
1.1 Cellular Neural/Nonlinear Netwo
Page 27 and 28:
1.2 Cellular Neural/Nonlinear Netwo
Page 29 and 30:
1.3 CNN-UM Implementations 9 the Lo
Page 31 and 32:
1.3 CNN-UM Implementations 11 modif
Page 33 and 34:
1.4 Field Programmable Gate Arrays
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
Page 41 and 42:
Page 43 and 44:
Page 45 and 46:
Page 47 and 48: 1.5 IBM Cell Broadband Engine Archi
Page 55 and 56: Chapter 2 Mapping the Numerical Sim
Page 57 and 58: 2.1 Introduction 37 18 Load instruc
Page 59 and 60: 2.1 Introduction 39 Instruction his
Page 61 and 62: 2.1 Introduction 41 2E+07 1E+07 9E+
Page 63 and 64: 2.1 Introduction 43 Main memory 8 t
Page 65 and 66: 2.1 Introduction 45 6 4.5 3 Speedup
Page 67 and 68: 2.1 Introduction 47 2.50E+07 1.88E+
Page 69 and 70: 2.2 Ocean model and its implementat
Page 71 and 72: 2.2 Ocean model and its implementat
Page 73 and 74: 2.3 Computational Fluid Flow Simula
Page 89 and 90: Chapter 3 Investigating the Precisi
Page 91 and 92: 3.2 Numerical Solutions of the PDEs
Page 93 and 94: 3.3 Testing Methodology 73 In fixed
Page 95 and 96: 3.4 Properties of the Arithmetic Un
Page 97: 3.4 Properties of the Arithmetic Un
Page 101 and 102: 3.5 Results 81 1E-02 1E-03 Error 1E
Page 103 and 104: 3.5 Results 83 arithmetic unit requ
Page 105: 3.6 Conclusion 85 point and the 40
Page 108 and 109: 4. IMPLEMENTING A GLOBAL ANALOGIC P
Page 130 and 131: 110 5. SUMMARY OF NEW SCIENTIFIC RE
Page 141 and 142: References The author’s journal p
Page 143 and 144: 5.2 Application of the results 123
show all

PPKE ITK PhD and MPhil Thesis Classes

Create successful ePaper yourself

Delete template?

Save as template?