PPKE ITK PhD and MPhil Thesis Classes

4. IMPLEMENTING A GLOBAL ANALOGIC PROGRAMMING UNIT
94 FOR EMULATED DIGITAL CNN PROCESSORS ON FPGA
4.3.2 Implementation of GAPU
The architecture of the GAPU is built up from five main components as shown
in Figure 4.3:
• MicroBlaze core,
• OPB bus (On-Chip Peripheral Bus),
• IPIF interface (Intellectual Property Interface),
• BRAM memories,
• Controller unit.
Additionally, it can be integrated with not only one, but several Falcon and Vector
processor elements in an array, which significantly increases the computing performance.
The number of the implementable processor is limited by the resources
of the development board.
The State-, Const- and Template-BRAM memories store the state, constant
and template values, respectively, while four special registers in the Controller
module (called Command, Status, IterCounter and IterLeft) implement common
functions in the instruction set processing. The Command register stores the
actual instruction, the Status register shows the status of the process, IterCounter
register stores the maximal number of iterations and the IterLeft register stores
the number of remaining iterations. These control signals controls the work of
the processors which are connected to the GAPU.
In our experimental system a Xilinx MicroBlaze core is attached to a Controller
unit across an IPIF interface (Intellectual Property InterFace). According
to the desired function, the Controller module generates control signals for operating
both Falcon and Vector processors. These processor elements can obtain data
from StateBRAM, ConstBRAM and TemplateBRAM memories implemented on
the dedicated on-chip BRAM memories, but storing larger pictures the external
on-board ZBT-SRAM modules might be used. The previously elaborated
Falcon processor is capable of performing a number of analog operations, while
arithmetical and logical instructions on the CNN array can be carried out by