PPKE ITK PhD and MPhil Thesis Classes

22 1. INTRODUCTION
1.4.4 Xilinx FPGAs
Xilinx FPGAs are belonging to the leading reconfigurable computers long ago.
Due to the fast Configurable Logic Blocks (CLB) and the large number of interconnections
arbitrary circuits can be implemented on it. In order to accelerate
certain operations dedicated elements (e.g.: digital signal processing (DSP)
blocks) are available on the FPGA. Throughout the dissertation all the used
FPGA platforms are made by Xilinx. In the next few sections the used FP-
GAs are going to introduced and a short outlook of the newest and future Xilinx
FPGAs are going to be shown.
1.4.4.1 Xilinx Virtex 2 FPGA
The first thing, which was implemented on the XC2V3000 Xilinx FPGA, was the
control unit (see in later chapters). The Virtex-II series FPGAs were introduced
in 2000. It was manufactured with 0.15 µm 8-layer metal process with 0.12 µm
high-speed transistors. Combining a wide variety of flexible features and a large
range of component densities up to 10 million system gates, the Virtex-II family
enhances programmable logic design capabilities and is a powerful alternative to
mask-programmed gates arrays.
There are several improvements compared to the former FPGAs. These improvements
include additional I/O capability by supporting more I/O standards,
additional memory capacity by using larger 18Kbit embedded block memories,
additional routing resources and embedded 18 × 18 bit signed multiplier blocks.
The XC2V3000 contains 3 million system gates which are organized to 64×56
array forming 14,336 slices. With the 96 18Kb SelectRAM blocks it can provide a
maximum of 1,728 Kbit RAM. The block SelectRAM memory resources are dualport
RAM, programmable from 16K x 1 bit to 512 x 36 bits, in various depth
and width configurations. Block SelectRAM memory is cascadable to implement
large embedded storage blocks. It has also 96 18 × 18 bit signed multiplier blocks
for accelerating multiplications.
The IOB, CLB, block SelectRAM, multiplier, and Digital Clock Management
(DCM) elements all use the same interconnect scheme and the same access to
the global routing matrix. There are a total of 16 global clock lines, with eight