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1.5 IBM Cell Broadband Engine Architecture 29
execute floating-point and Vector/SIMD Multimedia Extension instructions. The
Fixed-point Unit executes fixed-point operations, including add, multiply, divide,
compare, shift, rotate, and logical instructions. The Memory Management Unit
manages address translation for all memory accesses.
The EIB is not a bus as suggested by its name but a ring network which
contains 4 unidirectional rings where two rings run counter to the direction of
the other two. The EIB supports full memory-coherent and symmetric multiprocessor
(SMP) operations. Thus, a CBE processor is designed to be ganged
coherently with other CBE processors to produce a cluster. The EIB consists of
four 16-byte-wide data rings. Each ring transfers 128 bytes at a time. Processor
elements can drive and receive data simultaneously. The EIBŐs internal maximum
bandwidth is 96 bytes per processor-clock cycle. Multiple transfers can be
in-process concurrently on each ring, including more than 100 outstanding DMA
memory requests between main storage and the SPEs.
The on-chip Memory Interface Controller (MIC) provides the interface between
the EIB and physical memory. It supports one or two Rambus Extreme
Data Rate (XDR) memory interfaces, which together support between 64 MB
and 64 GB of XDR DRAM memory. Memory accesses on each interface are 1
to 8, 16, 32, 64, or 128 bytes, with coherent memory-ordering. Up to 64 reads
and 64 writes can be queued. The resource-allocation token manager provides
feedback about queue levels.
The dual-channel Rambus XDR memory interface provides very high 25.6GB/s
memory bandwidth. The XDR DRAM memory is ECC-protected, with multibit
error detection and optional single-bit error correction. I/O devices can be
accessed via two Rambus FlexIO interfaces where one of them (the Broadband
Interface (BIF)) is coherent and makes it possible to connect two Cell processors
directly.
The SPEs are SIMD only processors which are designed to handle streaming
data. Therefore they do not perform well in general purpose applications and
cannot run operating systems. Block diagram of the SPE is shown in Figure
1.14.
The SPE has two execution pipelines: the even pipeline is used to execute
floating point and integer instructions while the odd pipeline is responsible for