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16 1. INTRODUCTION apply an adequate voltage to change the structure of the crystal into a low resistance polycrystalline silicon-metal alloy. The transformation could not turned back and that is why it can be programmed only once. This technology is applied by Actel [35] and QuickLogic [36]. There are several memory based interconnection structure, which are commonly used by the larger FPGA manufacturers. The main advantage of these structures over the antifuse solution is the reprogrammability. This property gives the chance to the architecture designers to make rapid development of the architectures cost efficiently. The SRAM-based technology for FPGA configuration is commonly used by Xilinx [37] and Altera [38]. It contains 6 transistors, which stores the state of the interconnection. It has a great reliability and stores its value until the power is turned off. Three kind of basic building blocks are used in the structure of the programmable interconnections: multiplexor, pass transistor and tri-state buffer (see Figure 1.7). Figure 1.7: Basic programmable switches Usually multiplexers and pass transistors are used for the interconnections of the internal logical elements and all of the above are used for the external routing. (The use of the two, eight or more input multiplexer – depending on the complexity of the interconnections – is popular among the FPGAs.) The reason of the wiring inside of a logical cluster is follows: • implementation of low delay interconnections between the elements of the clusters,
1.4 Field Programmable Gate Arrays 17 • to develop a more complex element using the elements of the clusters, • non-programmable wiring for transferring fast carry bits for avoiding the extra delays when programmable interconnections (routing) are used. There are three main implementations for the global routing (which are used by the Xilinx by their FPGA family): row-based, symmetric (island) type and cellular architecture. Modern FPGA architectures are using significantly complex routing architectures, but their structures are based on these three. In case of the symmetric routing architecture the logical clusters are surrounded by segmented horizontal and vertical wiring channels, which can be seen in Figure 1.8. Figure 1.8: Symmetrical wiring Every cluster connects to the channels via ”connection box” and every segment in the routing can be interconnected to each other through a ”switch box”. The main property of this architecture is that the interconnection is made by segmented wires. This structure can be found on many Xilinx FPGA: furthermore Xilinx provides variable lengths for the segments and it provides the clusters with local connections for improving the efficiency of the architecture.
Page 1: An Optimal Mapping of Numerical Sim
Page 5 and 6: Acknowledgements It is not so hard
Page 7 and 8: Contents 1 Introduction 1 1.1 Cellu
Page 9: CONTENTS iii 4.3.3 Operating Steps
Page 12 and 13: vi LIST OF FIGURES 2.4 Performance
Page 15: List of Tables 2.1 Comparison of di
Page 18 and 19: xii LIST OF ABBREVIATIONS FPE Falco
Page 21 and 22: Chapter 1 Introduction Due to the r
Page 23 and 24: 3 can be represented in arbitrary t
Page 25 and 26: 1.1 Cellular Neural/Nonlinear Netwo
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2.3 Computational Fluid Flow Simula
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Chapter 3 Investigating the Precisi
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3.2 Numerical Solutions of the PDEs
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3.3 Testing Methodology 73 In fixed
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3.4 Properties of the Arithmetic Un
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3.4 Properties of the Arithmetic Un
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3.5 Results 79 in the L2 cache of t
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3.5 Results 81 1E-02 1E-03 Error 1E
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3.5 Results 83 arithmetic unit requ
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3.6 Conclusion 85 point and the 40
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4. IMPLEMENTING A GLOBAL ANALOGIC P
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110 5. SUMMARY OF NEW SCIENTIFIC RE
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References The author’s journal p
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5.2 Application of the results 123
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