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4. IMPLEMENTING A GLOBAL ANALOGIC PROGRAMMING UNIT 108 FOR EMULATED DIGITAL CNN PROCESSORS ON FPGA The implemented GAPU architecture, with the modified emulated digital Falcon architecture defines an organic like computing device, which builds up from simply, but large numbered of locally connected elements, which provides a distributed, decentralized, failure tolerant operation of the information processing.
Chapter 5 Summary of new scientific results 1. Development of an efficient mapping of the simulation of partial differential equations on inhomogenous and reconfigurable architectures: I have compared the optimal mapping of the simulation of a complex spatio-temporal dynamics on Xilinx Virtex FPGA and on IBM Cell architecture, and I made a framework for that. The framework has been successfully tested by the acceleration of a computational fluid dynamics (CFD) simulation. During the implementation my goal was always to reach the highest possible computational performance. The structure of the accelerator was designed according to this goal while considering the hardware specifications of the different architectures. • I have implemented an effective architecture, in the aspect of area, speed, dissipated power, bandwidth, for solving partial differential equations on structured grid. I have redesigned the arithmetic unit of the Falcon processor according to the discretized version of the partial differential equations optimized for the dedicated elements (BlockRAM, multiplier) of the FPGA. I have developed a process for the optimal bandwidth management between the processing elements and the memory on Xilinx Virtex and on IBM Cell architectures, which makes it possible to continuously supply the processing elements with data. 109
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An Optimal Mapping of Numerical Sim
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Acknowledgements It is not so hard
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Contents 1 Introduction 1 1.1 Cellu
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CONTENTS iii 4.3.3 Operating Steps
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vi LIST OF FIGURES 2.4 Performance
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List of Tables 2.1 Comparison of di
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xii LIST OF ABBREVIATIONS FPE Falco
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Chapter 1 Introduction Due to the r
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3 can be represented in arbitrary t
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1.1 Cellular Neural/Nonlinear Netwo
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1.2 Cellular Neural/Nonlinear Netwo
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1.3 CNN-UM Implementations 9 the Lo
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1.3 CNN-UM Implementations 11 modif
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1.4 Field Programmable Gate Arrays
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1.5 IBM Cell Broadband Engine Archi
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Chapter 2 Mapping the Numerical Sim
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2.1 Introduction 37 18 Load instruc
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2.1 Introduction 39 Instruction his
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2.1 Introduction 41 2E+07 1E+07 9E+
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2.1 Introduction 43 Main memory 8 t
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2.1 Introduction 45 6 4.5 3 Speedup
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2.1 Introduction 47 2.50E+07 1.88E+
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2.2 Ocean model and its implementat
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2.2 Ocean model and its implementat
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2.3 Computational Fluid Flow Simula
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2.3 Computational Fluid Flow Simula
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Page 141 and 142: References The author’s journal p
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