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vi LIST OF FIGURES 2.4 Performance of the implemented CNN simulator on the Cell architecture compared to other architectures, considering the speed of the Intel processor as a unit in both linear and nonlinear case (CNN cell array size: 256×256, 16 forward Euler iterations, *Core 2 Duo T7200 @2GHz, **Falcon Emulated Digital CNN-UM implemented on Xilinx Virtex-5 FPGA (XC5VSX95T) @550MHz only one Processing Element (max. 71 Processing Element). . . . . . . 40 2.5 Intruction histogram in case of one and multiple SPEs . . . . . . 41 2.6 Data-flow of the pipelined multi-SPE CNN simulator . . . . . . . 43 2.7 Instruction histogram in case of SPE pipeline . . . . . . . . . . . 44 2.8 Startup overhead in case of SPE pipeline . . . . . . . . . . . . . . 44 2.9 Speedup of the multi-SPE CNN simulation kernel . . . . . . . . . 45 2.10 Comparison of the instruction number in case of different unrolling 47 2.11 Performance comparison of one and multiple SPEs . . . . . . . . 48 2.12 The computational domain . . . . . . . . . . . . . . . . . . . . . . 56 2.13 Local store buffers . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.14 Data distribution between SPEs . . . . . . . . . . . . . . . . . . . 62 2.15 Number of slices in the arithmetic unit . . . . . . . . . . . . . . . 64 2.16 Number of multipliers in the arithmetic unit . . . . . . . . . . . . 65 2.17 Number of block-RAMs in the arithmetic unit . . . . . . . . . . . 66 2.18 Simulation around a cylinder in the initial state, 0.25 second, 0.5 second and in 1 second . . . . . . . . . . . . . . . . . . . . . . . . 67 3.1 Error of the 1st order scheme in different precision with 10 4 grid resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.2 The arithmetic unit of the first order scheme . . . . . . . . . . . . 76 3.3 The arithmetic unit of the second order scheme . . . . . . . . . . 77 3.4 Structure of the system with the accelerator unit . . . . . . . . . 78 3.5 Number of slices of the Accelerator Unit in different precisions . . 78 3.6 Error of the 1st order scheme in different precisions and step sizes using floating point numbers . . . . . . . . . . . . . . . . . . . . . 80 3.7 Error of the 2nd order scheme in different precisions and step sizes using floating point numbers . . . . . . . . . . . . . . . . . . . . . 81
LIST OF FIGURES vii 3.8 Error of the 1st order scheme in different precisions and step sizes using fixed-point numbers . . . . . . . . . . . . . . . . . . . . . . 82 3.9 Comparison of the different type of numbers and the different discretization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.1 The structure of the general Falcon processor element is optimized for GAPU integration. Main building blocks and signals with an additional low-level Control unit are depicted. . . . . . . . . . . . 90 4.2 Structure of the Falcon array based on locally connected processor elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.3 Detailed structure of the implemented experimental system (all blocks of GAPU are located within the dashed line). . . . . . . . . 95 4.4 Block diagram of the experimental system. The embedded GAPU is connected with Falcon and Vector processing elements on FPGA. 99 4.5 Results after some given iteration steps of the black and white skeletonization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.6 Number of required slices in different precision . . . . . . . . . . . 103 4.7 Number of required BlockRAMs in different precision . . . . . . . 104
Page 1: An Optimal Mapping of Numerical Sim
Page 5 and 6: Acknowledgements It is not so hard
Page 7 and 8: Contents 1 Introduction 1 1.1 Cellu
Page 9: CONTENTS iii 4.3.3 Operating Steps
Page 15: List of Tables 2.1 Comparison of di
Page 18 and 19: xii LIST OF ABBREVIATIONS FPE Falco
Page 21 and 22: Chapter 1 Introduction Due to the r
Page 23 and 24: 3 can be represented in arbitrary t
Page 25 and 26: 1.1 Cellular Neural/Nonlinear Netwo
Page 27 and 28: 1.2 Cellular Neural/Nonlinear Netwo
Page 29 and 30: 1.3 CNN-UM Implementations 9 the Lo
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Page 33 and 34: 1.4 Field Programmable Gate Arrays
Page 47 and 48: 1.5 IBM Cell Broadband Engine Archi
Page 55 and 56: Chapter 2 Mapping the Numerical Sim
Page 57 and 58: 2.1 Introduction 37 18 Load instruc
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2.1 Introduction 43 Main memory 8 t
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2.1 Introduction 45 6 4.5 3 Speedup
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2.1 Introduction 47 2.50E+07 1.88E+
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2.2 Ocean model and its implementat
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2.2 Ocean model and its implementat
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2.3 Computational Fluid Flow Simula
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Chapter 3 Investigating the Precisi
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3.2 Numerical Solutions of the PDEs
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3.3 Testing Methodology 73 In fixed
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3.4 Properties of the Arithmetic Un
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3.4 Properties of the Arithmetic Un
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3.5 Results 79 in the L2 cache of t
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3.5 Results 81 1E-02 1E-03 Error 1E
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3.5 Results 83 arithmetic unit requ
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3.6 Conclusion 85 point and the 40
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4. IMPLEMENTING A GLOBAL ANALOGIC P
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110 5. SUMMARY OF NEW SCIENTIFIC RE
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References The author’s journal p
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5.2 Application of the results 123
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