PPKE ITK PhD and MPhil Thesis Classes

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10 1. INTRODUCTION accelerator can be implemented either on multi-processor VLSI ASIC digital emulators (e.g CASTLE) [26], on DSP-, SPE-, and GPU-based hardware accelerator boards (e.g. CNN-HAC [27], Cell Broadband Engine Architecture [28], Nvidia Cuda [29], respectively), on FPGA-based reconfigurable computing architectures (e.g. FALCON [30]), as well. Generally, they speed up the software simulators, to get higher performance, but they are slower than the analog/mixed-signal CNN-UM implementations. A special Hardware Accelerator Board (HAB) was developed for simulating up to one-million-pixel arrays (with on-board memory) with four DSP (16 bit fixed point) chips. In fact, in a digital HAB, each DSP calculates the dynamics of a partition of the whole CNN array. Since for the calculation of the CNN dynamics a major part of DSP capability is not used, special purpose chips have been developed. The first emulated-digital, custom ASIC VLSI CNN-UM processor – called CASTLE.v1 – was developed in MTA-SZTAKI in Analogical and Neural Computing Laboratory between 1998 and 2001 for processing binary images [26], [31]. By using full-custom VLSI design methodology, this specialized systolic CNN array architecture greatly reduced the area requirements of the processor and makes it possible to implement multiple processing elements (with distributed ALUs) on the same silicon die. The second version of the CASTLE processor was elaborated with variable computing precision (1-bit ’logical’ and 6/12-bit ’bitvector’ processing modes), its structure can be expanded into an array of CASTLE processors. Moreover, it is capable of processing 240×320-sized images or videos at 25fps in real-time with low power dissipation (in mW range), as well. Emulated-digital approach can also benefit from scaling-down by using new manufacturing technologies to implement smaller and faster circuits with reduced power dissipation. Several fundamental attributes of the Falcon architecture [30] are based on CASTLE emulated-digital CNN-UM array processor architecture. However, the most important features which were greatly improved in this FPGA-based implementation are the flexibility of programming, the scalable accuracy of CNN computations, and configurable template size. Therefore, the majority of these
1.3 CNN-UM Implementations 11 modifications increased the performance. In case of CASTLE an important drawback was that its moderate (12-bits) precision is enough for image processing but not enough for some applications require more precise computations. Moreover, the array size is also fixed, which makes difficult to emulate large arrays, especially, when propagating cloning templates are used. To overcome these limitations configurable hardware description languages and reconfigurable devices (e.g. FPGA) were used to implement the FALCON architecture by employing rapid prototyping strategy [32]. This made it possible to increase the flexibility and create application optimized processor configurations. The configurable parameters are the following: • bit width of the state-, constant-, and template-values, • size of the cell array, • number and size of templates, • number and arrangement of the physical processor cores.
Page 1: An Optimal Mapping of Numerical Sim
Page 5 and 6: Acknowledgements It is not so hard
Page 7 and 8: Contents 1 Introduction 1 1.1 Cellu
Page 9: CONTENTS iii 4.3.3 Operating Steps
Page 12 and 13: vi LIST OF FIGURES 2.4 Performance
Page 15: List of Tables 2.1 Comparison of di
Page 18 and 19: xii LIST OF ABBREVIATIONS FPE Falco
Page 21 and 22: Chapter 1 Introduction Due to the r
Page 23 and 24: 3 can be represented in arbitrary t
Page 25 and 26: 1.1 Cellular Neural/Nonlinear Netwo
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Page 33 and 34: 1.4 Field Programmable Gate Arrays
Page 47 and 48: 1.5 IBM Cell Broadband Engine Archi
Page 55 and 56: Chapter 2 Mapping the Numerical Sim
Page 57 and 58: 2.1 Introduction 37 18 Load instruc
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Page 61 and 62: 2.1 Introduction 41 2E+07 1E+07 9E+
Page 63 and 64: 2.1 Introduction 43 Main memory 8 t
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Page 67 and 68: 2.1 Introduction 47 2.50E+07 1.88E+
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2.3 Computational Fluid Flow Simula
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Chapter 3 Investigating the Precisi
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3.2 Numerical Solutions of the PDEs
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3.3 Testing Methodology 73 In fixed
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3.4 Properties of the Arithmetic Un
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3.4 Properties of the Arithmetic Un
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3.5 Results 79 in the L2 cache of t
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3.5 Results 81 1E-02 1E-03 Error 1E
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3.5 Results 83 arithmetic unit requ
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3.6 Conclusion 85 point and the 40
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4. IMPLEMENTING A GLOBAL ANALOGIC P
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110 5. SUMMARY OF NEW SCIENTIFIC RE
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References The author’s journal p
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5.2 Application of the results 123
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