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4. IMPLEMENTING A GLOBAL ANALOGIC PROGRAMMING UNIT
102 FOR EMULATED DIGITAL CNN PROCESSORS ON FPGA
between the MicroBlaze core and the array of Falcon / Vector processor elements.
4.6 Device utilization
The experimental system is implemented on the RC203 development board from
Celoxica [75], which is equipped with a Xilinx Virtex-II 3000 FPGA including
14 336 slices, 96 18 × 18 bit signed multipliers, 96 BRAMs and 2 × 2 MB ZBT
SSRAM memory. Using rapid prototyping techniques and high-level hardware
description languages such as Handel-C from Celoxica makes it possible to develop
optimized architectures much faster, compared to the conventional VHDL or
Verilog based RTL-level approaches. During the implementation of the GAPU,
Handel-C is located at the top level of the design, while the MicroBlaze core
and its modules are wrapped as a low-level system processor macro. Using the
Platform Studio integrated development environment [37] from Xilinx supports
both the MicroBlaze soft-core and IBM PowerPC hard processor core designs.
The required number of resources of the Falcon Processor Element and the
proposed GAPU in different precision are examined (see Figure 4.6 and 4.7).
As shown in Table 4.1, the proposed GAPU, based on a Xilinx MicroBlaze
core, requires minimal additional area on the available chip resources at 18-bit
state precision, which accuracy is best suited for dedicated multipliers (MULT18×
18) and block-RAM (BRAM) modules. Though, the GAPU controller occupies
four-times as many slices and BRAMs as one Falcon PE does, but only a small
fraction of the available resources on the moderate-sized Virtex-II FPGA is used.
Due to this consideration, the embedded GAPU does not decrease the number
of implementable Falcon processor elements significantly. The number of the
implementable FPEs and VPEs is configurable. Hence, by using our XC2V3000
FPGA only 12% of the available slices are utilized, which makes it possible to
implement 15 FPE cores, depending on the limited number of BlockRAMs. We
can save some additional area by using external ZBT-SRAM modules instead
of on-chip BRAMs. Moreover, the speed of the GAPU is close to the clock
frequency of a Falcon processing element on Virtex-II architecture (the maximum
realizable clock frequency of the MicroBlaze core is shown in case of the stateof-the-art
Virtex-6 architecture [37]). If we want to attain the best performance,