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14 1. INTRODUCTION
interconnections, in case of many reconfigurable FPGA architectures, the logical
elements are arranged into clusters with fast and short-length wires. By using
fast interconnects of clusters more complex functions with even more input can
be implemented. Most LUT based architecture uses this strategy to form clusters
with two ore more 4 or 6 input logical elements, which are called configurable
logic block (CLB) in case of Xilinx FPGAs.
Basically the I/O architecture is the same in every FPGA family (see Figure
1.6). Mainly a tri-state buffer belongs to the output and an input buffer to
the input. One by one, the tri-state enable signal, the output signal and the input
signal can be registered and un-registered inside the I/O block, which depends
on the method of the configuration. The latest FPGAs are extended with many
new possibilities, which greatly increased the complexity of the basic structure.
For example the Xilinx Virtex-6 latest I/O properties are the following:
• Supports more than 50 I/O standards with properties like the Digitally
controlled impedance (DCI) active termination (for eliminating termination
resistance), or the flexible fine-grained I/O banking,
• Integrated interface blocks for PCI Express 2.0 designs,
• Programmable input delays.
1.4.2 Routing Interconnect
Similarly to the structure of the logical units, the FPGA developers designed
several solutions for interconnections. Basically the interconnections can be found
within the cluster (for generating complex functions) and out of the cluster too.
For that reason, the important properties of a connection are the following: low
parasitic resistance and capacitance, requires a small chip area, volatility, reprogrammability
and process complexity. Modern FPGAs are using two kind of
connection architectures, namely the antifuse and the memory-based architecture.
The main property of the antifuse technology is its small area and low parasitic
resistance and capacitance. It barriers the two metal layer with a nonconducting
amorphous silicon. If we want to make it conductive, we have to