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1.4 Field Programmable Gate Arrays 13
containing on-chip memory blocks and DSP blocks (dedicated multipliers, and
multiply/accumulator units).
Despite the fact that there are many FPGA families, the reconfigurable computers
are exclusively SRAM programmable devices. That means, the configuration
of the FPGA, the code as a generated ’bitfile’ – which defines the device
implemented algorithm – stored in an on-chip SRAM. With the loading of the
configurations into the SRAM memory different algorithms can be executed efficiently.
The configuration defines the logic function, which is computed by the
logic blocks and the interconnection-pattern.
From the mid 1980 the FPGA designers developed a number of programmable
logic structures into this architecture. The general structure is shown in Figure
1.5. This basic circuit contains programmable combination logic, synchronous
flip-flop (or asynchronous latch) and some fast carry logic, for decreasing the
need for area and delay dependency during the implementation. In this case the
output can be chosen randomly: it can be a combination logic, or flip-flop. It can
be also observed, that certain configuration uses memory for choosing the output
for the multiplexer.
Figure 1.5: General architecture of the programmable logic block
There are a number of design methodology for the implementation of the
combinational logic in the configurable logic block. Usually the configurable
combinational logic is implemented with memory (Look-Up Table, LUT), but
there are several architectures which uses multiplexers and logical gates instead
of memories. In order to decrease the trade-offs generated by the programmable