PPKE ITK PhD and MPhil Thesis Classes

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40 2. MAPPING THE NUMERICAL SIMULATIONS OF PARTIAL DIFFERENTIAL EQUATIONS 500 429 375 250 237 Speedup 125 64 123 104 0 6 12 21 35 1 1 5 1 SPE 2 SPEs 4 SPEs 8 SPEs Core 2 Duo*Falcon** Linear template Nonlinear template Figure 2.4: Performance of the implemented CNN simulator on the Cell architecture compared to other architectures, considering the speed of the Intel processor as a unit in both linear and nonlinear case (CNN cell array size: 256×256, 16 forward Euler iterations, *Core 2 Duo T7200 @2GHz, **Falcon Emulated Digital CNN-UM implemented on Xilinx Virtex-5 FPGA (XC5VSX95T) @550MHz only one Processing Element (max. 71 Processing Element). Linear template Nonlinear template 1 SPE 2 SPEs 4 SPEs 8 SPEs Core 2 Duo* Falcon** 6.3618533987 11.732637303 21.216215577 34.680960999 1 4.7809374462 63.858042696 122.88335743 236.97308812 429.17064116 1 104.42733765
2.1 Introduction 41 2E+07 1E+07 9E+06 6E+06 3E+06 Clock cycles 0E+00 SPE 1/1SPE 2/2SPE 4/2SPE 4/4SPE 8/2SPE 8/4SPE 8/6SPE 8/8 Single cycle Nop cycle Stall due to prefetch miss Stall due to waiting for hint target Dual cycle Stall due to branch miss Stall due to dependency Channel stall cycle Figure 2.5: Intruction histogram in case of one and multiple SPEs communication of the state values is required between the adjacent SPEs when the first or last line of the stripe is computed. Due to the row-wise arrangement of the state values, this communication between the adjacent SPEs can be carried out by a single DMA operation. Additionally, the ring structure of the EIB is well suited for the communication between neighboring SPEs. To measure the performance of the optimized program 16 iterations were computed on a 256×256 sized cell array. The number of required clock cycles is summarized in Figure 2.5. By using only one SPE, the computation is carried out in 3.3 million clock cycles or 1.04ms, assuming 3.2GHz clock frequency. If 2 SPEs are used to perform the computation, the cycle count is reduced about by half, and nearly linear speedup can be achieved. However, in case of 4 or 8 SPEs the performance cannot be improved. When 4 SPEs are used, SPE number 2 requires more than 5 million clock cycles to compute its stripe. This is larger than the cycle count in case of a single SPE and the performance is degraded. The examination of the utilization of the SPEs shows that SPE 1 and SPE 2 are stalled, most of the time, and wait for the completion of the memory
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An Optimal Mapping of Numerical Sim
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Acknowledgements It is not so hard
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Contents 1 Introduction 1 1.1 Cellu
Page 9: CONTENTS iii 4.3.3 Operating Steps
Page 12 and 13: vi LIST OF FIGURES 2.4 Performance
Page 15: List of Tables 2.1 Comparison of di
Page 18 and 19: xii LIST OF ABBREVIATIONS FPE Falco
Page 21 and 22: Chapter 1 Introduction Due to the r
Page 23 and 24: 3 can be represented in arbitrary t
Page 25 and 26: 1.1 Cellular Neural/Nonlinear Netwo
Page 27 and 28: 1.2 Cellular Neural/Nonlinear Netwo
Page 29 and 30: 1.3 CNN-UM Implementations 9 the Lo
Page 31 and 32: 1.3 CNN-UM Implementations 11 modif
Page 33 and 34: 1.4 Field Programmable Gate Arrays
Page 47 and 48: 1.5 IBM Cell Broadband Engine Archi
Page 55 and 56: Chapter 2 Mapping the Numerical Sim
Page 57 and 58: 2.1 Introduction 37 18 Load instruc
Page 59: 2.1 Introduction 39 Instruction his
Page 63 and 64: 2.1 Introduction 43 Main memory 8 t
Page 65 and 66: 2.1 Introduction 45 6 4.5 3 Speedup
Page 67 and 68: 2.1 Introduction 47 2.50E+07 1.88E+
Page 69 and 70: 2.2 Ocean model and its implementat
Page 71 and 72: 2.2 Ocean model and its implementat
Page 73 and 74: 2.3 Computational Fluid Flow Simula
Page 89 and 90: Chapter 3 Investigating the Precisi
Page 91 and 92: 3.2 Numerical Solutions of the PDEs
Page 93 and 94: 3.3 Testing Methodology 73 In fixed
Page 95 and 96: 3.4 Properties of the Arithmetic Un
Page 97 and 98: 3.4 Properties of the Arithmetic Un
Page 99 and 100: 3.5 Results 79 in the L2 cache of t
Page 101 and 102: 3.5 Results 81 1E-02 1E-03 Error 1E
Page 103 and 104: 3.5 Results 83 arithmetic unit requ
Page 105: 3.6 Conclusion 85 point and the 40
Page 108 and 109: 4. IMPLEMENTING A GLOBAL ANALOGIC P
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4. IMPLEMENTING A GLOBAL ANALOGIC P
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110 5. SUMMARY OF NEW SCIENTIFIC RE
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References The author’s journal p
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5.2 Application of the results 123
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PPKE ITK PhD and MPhil Thesis Classes

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