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1408 JOURNAL OF COMPUTERS, VOL. 8, NO. 6, JUNE 2013 new solution. State entry 9, 2, 3, and 7 from the best solution form part of new solution. State entry 8, 3, 9, 2, 4 and 6 from current solution form the other part of new solution. Modification of the new solution is carried out to make sure that duplicated state entry 2, 3, and 9 do not appear in the solution. By doing so, unassigned state entry 0, 1 and 5 are filled in. Figure 2. Exchange method. Figure 3. Swap method for two states close to each other. Figure 4. Swap method for two states apart from each other. D. Crossover Crossover operator is designed to escape the local optimum in the GA. In this paper crossover operator is adapted in the simulated annealing to generate a new solution by combining the best solution with the current solution. Consequently, some potential parts of the solution can be inherited from the previous solution. It operates as a position-based crossover [18]. An array of binary bits is initialised randomly, in which the length of the array equals to the length of the representation. When 1s appear in the array, copy the states from the best solution to new solution. When 0s appear in the array, copy the states from the current solution to new solution. Since each entry of state assignment solution is unique, continuous check is required avoiding the repetition of the same states which is not allowed. If state entry is duplicated, the first unassigned state entry is assigned. Figure 5 shows an example of relay operator to generate Figure 5. Crossover operator. E. Cost Function By minimising (6), low power dissipation could be achieved. Unfortunately, this may lead to area overhead, resulting in power overhead in the combinational part of the circuit. Therefore, objectives of area and power should be optimised simultaneously. The total cost function is C total = γC area + (1-γ) E, where C area is area function, E is power function and γ is a parameter specifying the tradeoff of E with respect to C area . F. Proposed Algorithm To begin with, an initiation solution is randomly produced. The annealing approach is divided into rough annealing and focusing annealing, which is identified by Temperature threshold T threshold . In the rough annealing stage the temperature is high and uses exchange method. In the focusing annealing stage the temperature is low and uses swap methods. The solution is evaluated by the cost function. The solution is accepted according to a probability P = exp (-∆C/T), where ∆C is the difference cost between new solution and current solution, T is the temperature. P is between 0 and 1. If the solution is improved and kept according to P, the new solution will be compared with the best recorded solution to decide whether updating the best record is necessary. If new solution is rejected instead, this solution is then ignored and reverses the current solution. Outer loop updates the temperature. The temperature schedules at each outer iteration. In the inner loop it generates possible solutions at each temperature. The algorithm terminates when reaching the lowest temperature and the output will be the best record. The pseudo code is shown in Algorithm 1. © 2013 ACADEMY PUBLISHER
JOURNAL OF COMPUTERS, VOL. 8, NO. 6, JUNE 2013 1409 Algorithm 1: Two stage Simulated Annealing Inputs: Temperature coefficient α Number of state variables N Exit temperature T 0 Temperature threshold T threshold Outputs: The best solution S best begin initialise a solution S current and temperature T while (T < T 0 ) { // outer loop k = 0 while (k < N 3 ) { // inner loop if (T > T threshold ) S new = generate solution via exchange method else S new = generate solution via swap methods k= k + 1 r = random (0, 1) ∆C = cost (S new ) – cost (S current ) if (r < exp (–∆C/T)) { S current = S new if (cost (S best ) > cost (S current )) S best = S current } } // end of inner loop T =αT } // end of outer loop Output the best solution S best IV. EXPERIMENTAL RESULTS The algorithm has been implemented in C++ and the results have been obtained on a personal computer with an INTEL CPU 2.4 GHz and 4 GB RAM. A Gaussian elimination method is used to find the total transition probabilities according to the STT of an FSM. ESSPRESSO is used to minimise the circuit for each state assignment. The product terms from this minimisation determine the number of cubes for that assignment. Switching activity is calculated by (6). T, T threshold and T 0 are set to 10000, 100 and 0.1, respectively. In order to balance the required solution quality and computational time, temperature schedule coefficient α is selected to 0.95 and 0.8 in the rough annealing stage and focusing annealing stage, respectively. Based on the numerous experimental results, when γ is 0.3, it performs the best trade-off between area and power consumption. The results are given in Table I, in which the first column shows the name of the circuit, the second column shows the number of states for the given circuit in the first column. Next three columns show comparison results among GA [8], MOGA [7] and the proposed method in terms of CPU time. The proposed method can convergence quicker than results compared to GA method in [8]. MOGA minimises the logical expressions via communication with ESSPRESSO, resulting that it takes significant more time than the proposed method. It can be seen in Table II that on average the proposed method produces results requiring 13.2% fewer product terms and 44.1% less switching activity compared to results obtained from NOVA [19]. Methods used in [20] and [21] achieve good power reduction but paying penalty of area consumption. MOGA [7] and GA [8] perform well in both area and power. The proposed algorithm outperforms other methods in both area saving and less power consumption in the tested suite. TABLE I. RECENTLY PUBLISHED RESULTS IN TERMS OF CPU TIME Circuits States GA[8] (s) MOGA[7] Ours (s) bbara 10 0.17 0h and 8 mins 0.12 cse 16 0.59 3hs and 9 mins 1.1 donfile 24 0.77 6hs and 4 mins 1.58 keyb 19 1.61 3hs and 32 mins 0.87 modulo12 12 0.13 5hs and 56 mins 0.15 planet 48 2.75 25hs and 23 mins 2.77 s1 20 4.37 6hs and 0 min 3.94 styr 30 4.44 6hs and 5 mins 2.57 ex1 20 3.26 6hs and 7 mins 2.68 ex4 14 0.27 6hs and 1 mins 0.38 opus 10 0.21 0h and 40 mins 0.22 Total 606 18.57 69h and 5 mins 16.38 V. CONCLUSIONS In the paper, two-stage simulated annealing based algorithm approach to the state assignment problem is proposed with the aim of minimising area and power dissipation for sequential circuits. By using designed twostage annealing approach, the algorithm is able to find the best assignment with fast convergence, which has reduced switching activity to minimise the power dissipation and the area simultaneously. By combing the best and current solutions, it utilises the experience of past solutions, overcoming the problem that ranking system in GA selection takes significant runtime. As a result, the algorithm outperforms the existing GA-based FSM state-encoding strategies achieving 13.2% fewer product terms and 44.1% less switch compared to NOVA and is therefore more suitable for area/power-optimised realisation of FSMs. ACKNOWLEDGMENT This work was supported by a grant (No. 11MS011) from State Key Lab of ASIC and System, China. REFERENCES [1] P. J. Wang, H. Li, “Low power mapping for AND/XOR circuits and its application in searching the best mixedpolarity,” Journal of Semiconductors, vol. 32, pp. 025007- 6, 2011. [2] S. N. Pradhan, M. T. Kumar, S. Chattopadhyay, “Low power finite state machine synthesis using power-gating,” Integration, the VLSI Journal, vol. 44, pp. 175-184, 2011. [3] P. J. Wang, J. G. Lu, X. Y. Zeng, “Searching the best polarity for low power based on WAGA,” Journal of CAD & Computer Graphics, vol. 20, pp. 73-78, 2008. © 2013 ACADEMY PUBLISHER
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Call for Papers and Special Issues
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(Contents Continued from Back Cover
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