Download Full Issue in PDF - Academy Publisher

More documents

Recommendations

Info

1410 JOURNAL OF COMPUTERS, VOL. 8, NO. 6, JUNE 2013 [4] T. Villa, T. Kam, R. Brayton, and A. Sangiovanni- Vincentelli, Synthesis of FSMs: Logic Optimisation Kluwer Academic Publishers, 1997. [5] J. H. Holland, Adaptation in Natural and Artificial Systems, University of Michigan Press, 1975. [6] A. E. A. Almaini, J. F. Miller, P. Thomson, and S. Billina, “State assignment of finite state machines using a genetic algorithm,” IEE Proc. Comput. Digit. Tech., vol. 142, pp. 279-286, 1995. [7] B. A. Al Jassani, N. Urquhart, A. E. A. Almaini, “State assignment for sequential circuits using multi-objective genetic algorithm,” IET Proc Comput. Digit. Tech., vol. 5, pp. 296-305, 2011. [8] Y. Xia, and A. E. A. Almaini, “Genetic algorithm based state assignment for power and area optimisation,” IET Proc Comput. Digit. Tech., vol. 149, pp. 128–133, 2002. [9] S. Chattopadhyay and P. Reddy, “Finite state machine state assignment targeting low power consumption,” IET Proc Comput. Digit. Tech., vol. 151, pp. 61–70, 2004. [10] S. Chattopadhyay, “Area conscious state assignment with flip flop and output polarity selection for finite state machine synthesis genetic algorithm approach,” Comput. J., vol. 48, pp. 443-450, 2005. [11] W. T. Shiue, “Novel state minimization and state assignment in finite state machine design for low power portable devices,” Integration. VLSI J., vol. 38, pp. 549- 570, 2005. [12] S. Goren and F. J. Ferguson, “On state reduction of incompletely specified finite state machines,” Computer Electr. Eng., vol. 33, pp. 58-69, 2007. [13] W. M. Aly, “Solving the state assignment problem using stochastic search aided with simulated annealing,” America J. Eng. Appl. Sci., vol. 2, pp. 710-714, 2009. [14] T. A. Dolotta, and E.J. McCluskey, “The coding of internal states of sequential circuits,” IEEE Trans. Electron. Comput., vol. EC-13, pp. 549-562, 1964. [15] S. Chattopadhyay, and P. N. Reddy, “Finite state machine state assignment targeting low power consumption,” IET Proc Comput. Digit. Tech., vol. 151, pp. 61-70, 2003. [16] Y. Q. Sheng, A. Takahashi, S. Ueno, “2-Stage Simulated Annealing with Crossover Operator for 3D-Packing Volume Minimization,” Proceedings of the 17th Workshop on Synthesis And System Integration of Mixed Information Technologies, pp. 227-232, 2012. [17] H. T. Wang; Z. J. Wang; J. Luo, “A simulated annealing algorithm for single container loading problem,” Proceedings of the 9th Intl. Conf. on Service Systems and Service Management, pp. 551-556, 2012. [18] A. E. A. Almaini, N. Zhuang, and F. Bourset, “Minimisation of multioutput Reed–Muller binary decision diagrams using hybrid genetic algorithm,” IEE Electron. Lett., vol. 31, pp. 1722-1723, 1995. [19] T. Villa, and A. Sangiovanni-Vincentelli, “NOVA: state assignment of finite state machine for optimal two-level logic implementation,” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., vol. 9, pp. 905-924, 1990. [20] S. K. Hong, I. C. Park, S. H. Hwang, and C. M. Kyung, “State assignment in finite state machines for minimal switching power consumption,” IEE Electron. Lett., vol. 30, pp. 627-629, 1994. [21] S. J. Wang, and M. D. Horng, “State assignment of finite state machines for low power applications,” IEE Electron. Lett., vol. 32, pp2323-2324, 1996. Meng Yang received Bachelor of Engineering (Honor) degree in Electrical Engineering from Shanghai University, Shanghai, China, in 1999. He received Master of Science with distinction in Electronics and Communication Engineering and Ph.D. in Electronics from School of Engineering Edinburgh Napier University, Edinburgh, UK, in 2002 and 2006, respectively. Currently he is a lecturer of Department of Microelectronics, School of Information Science and Technology, Fudan University, Shanghai, China. His research interests include algorithms in FPGA design automation, logic synthesis, and dynamic reconfigurable FPGA automation design. He has published more than 30 research papers. Dr. Yang is a member of IET and Chairman of Young Member Section of IET Shanghai Branch. TABLE II. EXPERIMENTAL RESULTS SHOWING POWER AND AREA IN COMPARISON Circuits NOVA[19] MOGA[7] GA[8] Hong[20] Wang[21] This paper area Power area power area Power Area power area power area Power bbara 24 0.495 22 0.49 22 0.317 26 0.295 26 0.279 22 0.277 bbsse 30 1.5 28 0.663 27 0.783 31 0.856 31 0.776 27 0.758 cse 46 0.604 43 0.39 43 0.355 50 0.292 48 0.239 43 0.250 donfile 28 1.75 22 1.375 36 1.6 40 1.083 45 1.125 22 1.458 keyb 48 1.466 46 0.98 46 0.674 52 0.647 58 0.556 46 0.533 modulo12 12 1 10 0.75 12 0.583 12 0.583 12 0.5 10 0.568 planet 87 2.831 81 2.49 86 2.424 101 1.153 103 0.984 81 1.680 s1 80 1.698 43 1.37 66 1.48 85 1.131 91 1.175 43 1.188 sand 97 1.085 94 0.585 89 0.765 110 0.604 109 0.61 92 0.666 styr 94 1.278 78 1.1 88 0.943 101 0.578 99 0.553 78 0.578 ex1 44 1.358 48 0.78 52 0.842 49 0.755 47 1.135 48 0.754 ex4 19 1.316 13 0.568 14 0.421 16 0.495 18 0.957 13 0.476 opus 16 0.812 15 0.49 15 0.556 17 0.524 17 0.712 15 0.471 train11 9 0.619 10 0.414 10 0.339 9 0.36 10 0.714 10 0.302 Total 634 17.812 553 12.445 606 12.082 699 9.356 714 10.315 550 9.959 Improved% 0% 0% -13% -30% -4% -32% 10% -47% 13% -42% -13.2% -44.1% © 2013 ACADEMY PUBLISHER
JOURNAL OF COMPUTERS, VOL. 8, NO. 6, JUNE 2013 1411 A Rotation-based Data Buffering Architecture for Convolution Filtering in a Field Programmable Gate Array Zhijian Lu College of Computer Science and Technology Harbin Engineering University, Harbin, China Email: luzhijian@hrbeu.edu.cn Yanxia Wu, Zhenhua Guo, Guochang Gu College of Computer Science and Technology Harbin Engineering University, Harbin, China Email: {wuyanxia, guozhenhua, guguochang}@hrbeu.edu.cn Abstract—Convolution filtering applications range from image recognition and video surveillance. Two observations drive the design of a new buffering architecture for convolution filters. First, the convolutional operations are inherently local; hence every pixel of the output feature maps is calculated by the neighboring pixels of the input feature maps. Even though the operation is simple, the convolution filtering is both computation-intensive and memory-intensive. For real-time applications, large amounts of on-chip memories are required to support massively parallel processing architectures. Second, to avoid access to external memories directly, the data that are already stored in on-chip memories should be used as many times as possible. Based on these two observations, we show that for a given throughput rate and off-chip memory bandwidth, a rotation-based data buffering architecture provide the optimum area-utilization results for a particular design point, which are commonly used applications in recognition area. Index Terms—convolution filtering, Field Programmable Gate Arrays (FPGAs), data buffering I. INTRODUCTION Convolution filters are the computational models that are widely used in recognition and video processing domains [1][2][3][4]. The computation of convolution requires not only the high computational capability but also large memory bandwidth, especially when high-definition images and videos have to be processed in real-time. In these applications, convolution filtering plays an essential role [5][6]. Generally, external memories are used to contain input image pixels, but the memory bandwidth cannot satisfy the requirement of the optimal throughput directly. Hence intermediate buffers by means of on-chip memories are adopted to avoid access to external memories directly [7][8]. To load as many pixel values as needed to the convolution filter in one cycle, multiple memory ports are attached to intermediate data buffers. Once a pixel value is loaded, it can be reused for the corresponding successive convolutions to avoid accessing it from off-chip memories repetitively. As a result, the requirements for off-chip memory bandwidth are reduced. Convolution architecture with a complete convolution architecture is adopted in [7], where a set of linear shift registers are used to move a window over the input image. The input image is divided in rows, each with a fixed length according to the input image row length, and the height according to the convolution window height. Each pixel in the input image needs to be loaded only once to the intermediate data buffer and with a fixed minimum external memory bandwidth. In case the size of input image or convolution window become large, FPGA implementations become very expensive, which will cost a significant amount of FPGA resources [7][8]. There are alternative buffering architectures that internal buffers only store a small portion of pixels [7][9]. Each group of shift registers in the convolution window receives the pixels belonging to consecutive rows of input image. Compared with the aforementioned methods, a great shift register reduction is achieved. However, multiple-dataflow is needed to feed data to the internal buffer. Pixels in the input image need to be read repetitively from external memories depending on the size of convolution window. And to keep the maximum throughput rate, this leads to a sharp increase in terms of external memory bandwidth requirement. In this paper, we are concerned with the implementation of convolution filters in FPGA and we design a alternative buffering architecture for convolution filters that shows good balance between on-chip resource utilization and external memory bus bandwidth. II. ROTATION-BASED DATA BUFFERING ARCHITECTURE Yanxia Wu is the corresponding author. © 2013 ACADEMY PUBLISHER doi:10.4304/jcp.8.6.1411-1416
Page 1 and 2: Journal of Computers ISSN 1796-203X
Page 3: Corn Moisture Measurement using a C
Page 6 and 7: 1378 JOURNAL OF COMPUTERS, VOL. 8,
Page 88 and 89:
1460 JOURNAL OF COMPUTERS, VOL. 8,
Page 90 and 91:
Page 92 and 93:
Page 94 and 95:
Page 96 and 97:
Page 98 and 99:
Page 100 and 101:
Page 102 and 103:
Page 104 and 105:
Page 106 and 107:
Page 108 and 109:
Page 110 and 111:
Page 112 and 113:
Page 114 and 115:
Page 116 and 117:
Page 118 and 119:
Page 120 and 121:
Page 122 and 123:
Page 124 and 125:
Page 126 and 127:
Page 128 and 129:
Page 130 and 131:
Page 132 and 133:
Page 134 and 135:
Page 136 and 137:
Page 138 and 139:
Page 140 and 141:
Page 142 and 143:
Page 144 and 145:
Page 146 and 147:
Page 148 and 149:
Page 150 and 151:
Page 152 and 153:
Page 154 and 155:
Page 156 and 157:
Page 158 and 159:
Page 160 and 161:
Page 162 and 163:
Page 164 and 165:
Page 166 and 167:
Page 168 and 169:
Page 170 and 171:
Page 172 and 173:
Page 174 and 175:
Page 176 and 177:
Page 178 and 179:
Page 180 and 181:
Page 182 and 183:
Page 184 and 185:
Page 186 and 187:
Page 188 and 189:
Page 190 and 191:
Page 192 and 193:
Page 194 and 195:
Page 196 and 197:
Page 198 and 199:
Page 200 and 201:
Page 202 and 203:
Page 204 and 205:
Page 206 and 207:
Page 208 and 209:
Page 210 and 211:
Page 212 and 213:
Page 214 and 215:
Page 216 and 217:
Page 218 and 219:
Page 220 and 221:
Page 222 and 223:
Page 224 and 225:
Page 226 and 227:
Page 228 and 229:
Page 230 and 231:
Page 232 and 233:
Page 234 and 235:
Page 236 and 237:
Page 238 and 239:
Page 240 and 241:
Page 242 and 243:
Page 244 and 245:
Page 246 and 247:
Page 248 and 249:
Page 250 and 251:
Page 252 and 253:
Page 254 and 255:
Page 256 and 257:
Page 258 and 259:
Page 261:
Call for Papers and Special Issues
Page 264:
(Contents Continued from Back Cover
show all

Download Full Issue in PDF - Academy Publisher

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?