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1414 JOURNAL OF COMPUTERS, VOL. 8, NO. 6, JUNE 2013
Figure 4. R simultaneous convolution windows in a area
off-chip memory
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I
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O
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column 1 column S-1 column S column Y
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. . .
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R . . . 1
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convolution filter array
Figure 5. Rotation-based data buffering architecture
convolution architecture the window in the rotation-based
architecture is updated every cycle. In this case, shift
registers can move every cycles. pixels in all will be
loaded from off-chip memories every cycles. So the
external memory bandwidth is / pixels/clock. This
means that for most convolution filter applications approximately
twice of the external memory bandwidth
requirement is needed.
III. ARCHITECTURE SELECTION
In this section, we will consider an input image size of
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