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Philips Semiconductors Preliminary User Manual ARM-based Microcontroller I 2 C Bus PIN DESCRIPTION Table 92: I 2 C Pin Description SDA SCL LPC2131/2132/2138 I 2 C OPERATING MODES Figure 18: I 2 C Bus Configuration Pin Name Type Description SDA0,1 Input/Output I 2 C Serial Data. SCL0,1 Input/Output I 2 C Serial Clock. LPC2131/2132/2138 In a given application, the I 2 C block may operate as a master, a slave, or both. In the slave mode, the I 2 C hardware looks for its own slave address and the general call address. If one of these addresses is detected, an interrupt is requested. If the processor wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave operation is not interrupted. If bus arbitration is lost in the master mode, the I 2 C block switches to the slave mode immediately and can detect its own slave address in the same serial transfer. Master Transmitter Mode: Pullup Resistor Pullup Resistor Other Device with I 2 C Interface Other Device with I 2 C Interface In this mode data is transmitted from master to slave. Before the master transmitter mode can be entered, the I2CONSET register must be initialized as shown in Figure 19. I2EN must be set to 1 to enable the I 2 C function. If the AA bit is 0, the I 2 C interface will not acknowledge any address when another device is master of the bus, so it can not enter slave mode. The STA, STO and SI bits must be 0. The SI Bit is cleared by writing 1 to the SIC bit in the I2CONCLR register. I2C Interfaces I2C0 and I2C1 116 November 22, 2004 SDA SCL
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller I2CONSET - I2EN STA STO SI AA - - Figure 19: Master Mode Configuration LPC2131/2132/2138 The first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. In this mode the data direction bit (R/W) should be 0 which means Write. The first byte transmitted contains the slave address and Write bit. Data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received. START and STOP conditions are output to indicate the beginning and the end of a serial transfer. The I 2 C interface will enter master transmitter mode when software sets the STA bit. The I 2 C logic will send the START condition as soon as the bus is free. After the START condition is transmitted, the SI bit is set, and the status code in the I2STAT register is 08h. This status code is used to vector to a state service routine which will load the slave address and Write bit to the I2DAT register, and then clear the SI bit. SI is cleared by writing a 1 to the SIC bit in the I2CONCLR register. When the slave address and R/W bit have been transmitted and an acknowledgment bit has been received, the SI bit is set again, and the possible status codes now are 18h, 20h, or 38h for the master mode, or 68h, 78h, or 0B0h if the slave mode was enabled (by setting AA 1). The appropriate actions to be taken for each of these status codes are shown in Table 102 to Table 105. Master Receiver Mode: 7 6 5 4 3 2 1 0 - 1 0 0 0 0 - - S Slave Address R/W A DATA A DATA A/A P From Master to Slave From Slave to Master "0" - Write "1" - Read Data Transferred (n Bytes + Acknowledge) A = Acknowledge (SDA low) A = Not Acknowledge (SDA high) S = START condition P = STOP Condition Figure 20: Format in the master transmitter mode In the master receiver mode, data is received from a slave transmitter. The transfer is initiated in the same way as in the master transmitter mode. When the START condition has been transmitted, the interrupt service routine must load the slave address and the data direction bit to the I 2 C Data Register (I2DAT), and then clear the SI bit. In this case, the data direction bit (R/W) should be 1 to indicate a read. When the slave address and data direction bit have been transmitted and an acknowledge bit has been received, the SI bit is set, and the Status Register will show the status code. For master mode, the possible status codes are 40H, 48H, or 38H. For slave mode, the possible status codes are 68H, 78H, or B0H. For details, refer to Table 103. I2C Interfaces I2C0 and I2C1 117 November 22, 2004
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