LPC2131/2132/2138 User Manual - mct.net

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Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2131/2132/2138 The LPC2131/2132/2138 Flash memory provides minimum of 10,000 erase/write cycles and 10 years of data-retention. ON-CHIP STATIC RAM On-Chip static RAM (SRAM) may be used for code and/or data storage. The SRAM may be accessed as 8-bits, 16-bits, and 32bits. The LPC2131/2132/2138 provide 8/16/32 kB of static RAM respectively. The LPC2131/LPC2132/2138 SRAM is designed to be accessed as a byte-addressed memory. Word and halfword accesses to the memory ignore the alignment of the address and access the naturally-aligned value that is addressed (so a memory access ignores address bits 0 and 1 for word accesses, and ignores bit 0 for halfword accesses). Therefore valid reads and writes require data accessed as halfwords to originate from addresses with address line 0 being 0 (addresses ending with 0, 2, 4, 6, 8, A, C, adnd E) and data accessed as words to originate from adresses with address lines 0 and 1 being 0 (addresses ending with 0, 4, 8, and C). This rule applies to both off and on-chip memory usage. The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls during back-to-back writes. The write-back buffer always holds the last data sent by software to the SRAM. This data is only written to the SRAM when another write is requested by software (the data is only written to the SRAM when software does another write). If a chip reset occurs, actual SRAM contents will not reflect the most recent write request (i.e. after a "warm" chip reset, the SRAM does not reflect the last write operation). Any software that checks SRAM contents after reset must take this into account. Two identical writes to a location guarantee that the data will be present after a Reset. Alternatively, a dummy write operation before entering idle or power-down mode will similarly guarantee that the last data written will be present in SRAM after a subsequent Reset. Introduction 18 November 22, 2004
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller BLOCK DIAGRAM Internal SRAM Controller 8/16/32 kB SRAM EINT3:0 8 x CAP0 8 x MAT AD0.7:0 AD1.7:0 2 A out 3 P0.31:0 P1.31:16, 1:02 PWM6:1 1 Shared with GPIO. 2 LPC2138 only. 3 LPC2132/2138 only. ARM7 Local Bus Internal Flash Controller 32/64/512 kB FLASH External Interrupts Capture / Compare (w/ external clock) TIMER 0 & 1 A/D Converters 0 and 1 2 D/A Converter 2 General Purpose I/O PWM0 TRST1 TMS 1 TCK 1 Test/Debug Interface ARM7TDMI-S AMBA AHB (Advanced High-performance Bus) VPB (VLSI Peripheral Bus) Figure 1: LPC2131/2132/2138 Block Diagram I 2 C Serial Interfaces 0 and 1 LPC2131/2132/2138 Vectored Interrupt Controller AHB Decoder Introduction 19 November 22, 2004 TDI 1 TDO 1 AHB Bridge AHB to VPB Bridge Emulation Trace Module VPB Divider System Clock PLL SPI and SSP Serial Interfaces UART 0 & 1 Real Time Clock Watchdog Timer System Control Xtal2 RESET Xtal1 System Functions SCL0,1 SDA0,1 SCK0,1 MOSI0,1 MISO0,1 SSEL0,1 TxD0,1 RxD0,1 DSR1 2 ,CTS1 2 ,RTS1 2 DTR1 2 , DCD1 2 ,RI1 2 RTXC1 RTXC2 V bat
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