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Philips Semiconductors Preliminary User Manual ARM-based Microcontroller PIN DESCRIPTIONS Table 143: A/D Pin Description Pin Name Type Pin Description AD0.7:0 & AD1.7:0 (LPC2138) Input REGISTER DESCRIPTION LPC2131/2132/2138 Analog Inputs. The A/D converter cell can measure the voltage on any of these input signals. Note that these analog inputs are always connected to their pins, even if the Pin Multiplexing Register assigns them to port pins. A simple self-test of the A/D Converter can be done by driving these pins as port outputs. Note: if the A/D converter is used, signal levels on analog input pins must not be above the level of V 3A at any time. Otherwise, A/D converter readings will be invalid. If the A/D converter is not used in an application then the pins associated with A/D inputs can be used as 5V tolerant digital IO pins. V ref Reference Voltage Reference. This pin is connected to the VrefP signals of both A/D converters. V DDA , V SSA Power The base address of the A/D Converter is 0xE003 4000 (page 24). The A/D Converter includes 2 registers as shown in Table 144. Table 144: A/D Registers Generic Name ADCR ADDR ADGSR Analog Power and Ground. These should be nominally the same voltages as V 3 and V SSD , but should be isolated to minimize noise and error. Description Access Reset Value A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur. A/D Data Register. This register contains the ADC’s DONE bit and (when DONE is 1) the 10-bit result of the conversion. A/D Global Start Register. This address can be written (in the AD0 address range) to start conversions in both A/D converters simultaneously. Read/Write 0x0000 0001 Read/Write NA Write Only 0x00 AD0 Address & Name 0xE003 4000 AD0CR 0xE003 4004 AD0DR ADGSR 0xE003 4008 AD1 Address & Name 0xE006 0000 AD1CR 0xE006 0004 AD1DR A/D Converter 198 November 22, 2004
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller A/D Control Register (AD0CR - 0xE0034000, AD1CR - 0xE0060000) Table 145: A/D Control Register (AD0CR - 0xE0034000, AD1CR - 0xE0060000) LPC2131/2132/2138 ADCR Name Description Reset Value 7:0 SEL 15:8 CLKDIV 16 BURST 19:17 CLKS 21 PDN 23:22 TEST1:0 26:24 START 27 EDGE 31:28 Reserved Selects which of the AD0.7:0/AD1.7:0 pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0.0, and bit 7 selects pin AD0.7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01. The VPB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. If this bit is 0, conversions are software controlled and require 11 clocks. If this bit is 1, the AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that’s in progress when this bit is cleared will be completed. This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits): 000=11 clocks/10 bits, 001=10 clocks/9 bits,..., 111=4 clocks/3 bits 1: the A/D converter is operational 0: the A/D converter is in power down mode These bits are used in device testing. 00=normal operation, 01=digital test mode, 10=DAC test mode, and 11=simple conversion test mode. When the BURST bit is 0, these bits control whether and when an A/D conversion is started: 000: no start (this value should be used when clearing PDN to 0) 001: start conversion now 010: start conversion when the edge selected by bit 27 occurs on P0.16/EINT0/MAT0.2/ CAP0.2 011: start conversion when the edge selected by bit 27 occurs on P0.22/TD3/CAP0.0/ MAT0.0 Note: for choices 100-111 the MAT signal need not be pinned out: 100: start conversion when the edge selected by bit 27 occurs on MAT0.1 101: start conversion when the edge selected by bit 27 occurs on MAT0.3 110: start conversion when the edge selected by bit 27 occurs on MAT1.0 111: start conversion when the edge selected by bit 27 occurs on MAT1.1 This bit is significant only when the START field contains 010-111. In these cases: 0: start conversion on a falling edge on the selected CAP/MAT signal 1: start conversion on a rising edge on the selected CAP/MAT signal User software should not write ones to reserved bits. The value read from a reserved bit is not defined. A/D Converter 199 November 22, 2004 0x01 0 0 000 0 0 000 0 0
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