LPC2131/2132/2138 User Manual - mct.net

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Philips Semiconductors Preliminary User Manual ARM-based Microcontroller REGISTER DESCRIPTION The SPI contains 5 registers as shown in Table 109. All registers are byte, half word and word accessible. Table 109: SPI Register Map Generic Name *Reset Value refers to the data stored in used bits only. It does not include reserved bits content. SPI Control Register (S0SPCR - 0xE0020000) Description Access SPCR SPI Control Register. This register controls the operation of the SPI. SPSR SPI Status Register. This register shows the status of the SPI. SPDR SPCCR SPINT SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI by writing to this register. Data received by the SPI can be read from this register. SPI Clock Counter Register. This register controls the frequency of a master’s SCK. SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. The SPCR register controls the operation of the SPI as per the configuration bits setting. Table 110: SPI Control Register (S0SPCR - 0xE0020000) SPCR Function Description 2:0 Reserved 3 CPHA LPC2131/2132/2138 Reset Value* SPI0 Address & Name SPI Interface (SPI0) 158 November 22, 2004 Read/ Write Read Only Read/ Write Read/ Write Read/ Write Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending. When 1, data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active. When 0, data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal. 0 0 0 0 0 0xE0020000 S0SPCR 0xE0020004 S0SPSR 0xE0020008 S0SPDR 0xE002000C S0SPCCR 0xE002001C S0SPINT 4 CPOL Clock polarity control. When 1, SCK is active low. When 0, SCK is active high. 0 5 MSTR 6 LSBF 7 SPIE Master mode select. When 1, the SPI operates in Master mode. When 0, the SPI operates in Slave mode. LSB First controls which direction each byte is shifted when transferred. When 1, SPI data is transferred LSB (bit 0) first. When 0, SPI data is transferred MSB (bit 7) first. Serial peripheral interrupt enable. When 1, a hardware interrupt is generated each time the SPIF or MODF bits are activated. When 0, SPI interrupts are inhibited. Reset Value NA 0 0 0 0
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller SPI Status Register (S0SPSR - 0xE0020004) The SPSR register controls the operation of the SPI as per the configuration bits setting. Table 111: SPI Status Register (S0SPSR - 0xE0020004) SPSR Function Description 2:0 Reserved 3 ABRT 4 MODF 5 ROVR 6 WCOL 7 SPIF SPI Data Register (S0SPDR - 0xE0020008) LPC2131/2132/2138 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. This bi-directional data register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI by writing to this register. Data received by the SPI can be read from this register. When a master, a write to this register will start a SPI data transfer. Writes to this register will be blocked from when a data transfer starts to when the SPIF status bit is set, and the status register has not been read. Table 112: SPI Data Register (S0SPDR - 0xE0020008) Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register. Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI control register. Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register. Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI data register. SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI data register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register. SPDR Function Description 7:0 Data SPI Bi-directional data port 0 SPI Clock Counter Register (S0SPCCR - 0xE002000C) Reset Value This register controls the frequency of a master’s SCK. The register indicates the number of pclk cycles that make up an SPI clock. The value of this register must always be an even number. As a result, bit 0 must always be 0. The value of the register must also always be greater than or equal to 8. Violations of this can result in unpredictable behavior. Table 113: SPI Clock Counter Register (S0SPCCR - 0xE002000C) SPCCR Function Description 7:0 Counter SPI Clock counter setting 0 SPI Interface (SPI0) 159 November 22, 2004 NA 0 0 0 0 0 Reset Value Reset Value
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