LPC2131/2132/2138 User Manual - mct.net

Philips Semiconductors Preliminary User Manual
ARM-based Microcontroller
SCK (CPOL = 0)
SCK (CPOL = 1)
SSEL
CPHA = 0
Cycle # CPHA = 0
MOSI (CPHA = 0)
MISO (CPHA = 0)
CPHA = 1
Cycle # CPHA = 1
MOSI (CPHA = 1)
MISO (CPHA = 1)
Bit 1
Figure 36: SPI Data Transfer Format (CPHA = 0 and CPHA = 1)
LPC2131/2132/2138
The data and clock phase relationships are summarized in Table 107. This table summarizes the following for each setting of
CPOL and CPHA.
When the first data bit is driven.
When all other data bits are driven.
When data is sampled.
Table 107: SPI Data To Clock Phase Relationship
1 2 3 4 5 6 7 8
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
1 2 3 4 5 6 7 8
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
CPOL And CPHA Settings First Data Driven Other Data Driven Data Sampled
CPOL = 0, CPHA = 0 Prior to first SCK rising edge SCK falling edge SCK rising edge
CPOL = 0, CPHA = 1 First SCK rising edge SCK rising edge SCK falling edge
CPOL = 1, CPHA = 0 Prior to first SCK falling edge SCK rising edge SCK falling edge
CPOL = 1, CPHA = 1 First SCK falling edge SCK falling edge SCK rising edge
The definition of when an 8 bit transfer starts and stops is dependent on whether a device is a master or a slave, and the setting
of the CPHA variable.
SPI Interface (SPI0) 154 November 22, 2004