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Philips Semiconductors Preliminary <strong>User</strong> <strong>Manual</strong><br />
ARM-based Microcontroller<br />
FLASH CONTENT PROTECTION MECHANISM<br />
<strong>LPC2131</strong>/<strong>2132</strong>/<strong>2138</strong><br />
The <strong>LPC2131</strong>/<strong>2132</strong>/<strong>2138</strong> is equipped with the Error Correction Code (ECC) capable Flash memory. The purpose of an error<br />
correction module is twofold. Firstly, it decodes data words read from the memory into output data words. Secondly, it encodes<br />
data words to be written to the memory. The error correction capability consists of single bit error correction with Hamming code.<br />
The operation of ECC is transparent to the running application. The ECC content itself is stored in a flash memory not accessible<br />
by user’s code to either read from it or write into it on its own. A byte of ECC corresponds to every consecutive 128 bits of the<br />
user accessible Flash. Consequently, Flash bytes from 0x0000 0000 to 0x0000 0003 are protected by the first ECC byte, Flash<br />
bytes from 0x0000 0004 to 0x0000 0007 are protected by the second ECC byte, etc.<br />
Whenever the CPU requests a read from user’s Flash, both 128 bits of raw data containing the specified memory location and<br />
the matching ECC byte are evaluated. If the ECC mechanism detects a single error in the fetched data, a correction will be<br />
applied before data are provided to the CPU. When a write request into the user’s Flash is made, write of user specified content<br />
is accompanied by a matching ECC value calculated and stored in the ECC memory.<br />
When a sector of user’s Flash memory is erased, corresponding ECC bytes are also erased. Once an ECC byte is written, it can<br />
not be updated unless it is erased first. Therefore, for the implemented ECC mechanism to perform properly, data must be written<br />
into the Flash memory in groups of 4 bytes (or multiples of 4), aligned as described above.<br />
CODE READ PROTECTION<br />
Code read protection is enabled by programming the flash address location 0x1FC (<strong>User</strong> flash sector 0) with value 0x87654321<br />
(2271560481 Decimal). Address 0x1FC is used to allow some room for the fiq exception handler. When the code read protection<br />
is enabled the JTAG debug port, external memory boot and the following ISP commands are disabled:<br />
Read Memory<br />
Write to RAM<br />
Go<br />
Copy RAM to Flash<br />
The ISP commands mentioned above terminate with return code CODE_READ_PROTECTION_ENABLED.<br />
The ISP erase command only allows erasure of all user sectors when the code read protection is enabled. This limitation does<br />
not exist if the code read protection is not enabled. IAP commands are not affected by the code read protection.<br />
Important: code read protection is active/inactive once the device has gone through a power cycle.<br />
Flash Memory System and Programming 230 November 22, 2004
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