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Philips Semiconductors Preliminary User Manual ARM-based Microcontroller SSP Control Register 1 (SSPCR1 - 0xE0068004) This register controls certain aspects of the operation of the SSP controller. Table 118: SSP Control Register 1 (SSPCR1 - 0xE0068004) SSPCR1 Name Description 3 SOD 2 MS 1 SSE 0 LBM SSP Data Register (SSPDR - 0xE0068008) Software can write data to be transmitted to this register, and read data that has been received. Table 119: SSP Data Register (SSPDR - 0xE0068008) LPC2131/2132/2138 Slave Output Disable. This bit is relevant only in slave mode (MS=1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO). Master/Slave Mode. A 0 in this bit (as after Reset) makes the SSP controller act as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line. A 1 in this bit makes the SSP controller act as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines. This bit can only be written when the SSE bit is 0. (One can set MS and SSE to 1 simultaneously). SSP Enable. When this bit is 1, the SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit. Loop Back Mode. This bit should be 0 for normal operation. When it is 1, serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively). SSPDR Name Description 15:0 DATA Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s. Reset Value SSP Controller (SPI1) 172 November 22, 2004 0 0 0 0 Reset Value 0
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller SSP Status Register (SSPSR - 0xE006800C) This read-only register reflects the current status of the SSP controller. Table 120: SSP Status Register (SSPSR - 0xE006800C) SSPSR Name Description SSP Clock Prescale Register (SSPCPSR - 0xE0068010) LPC2131/2132/2138 4 BSY Busy. This bit is 0 if the SSP controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. 0 3 RFF Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. 0 2 RNE Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. 0 1 TNF Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 1 0 TFE Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. 1 This register controls the factor by which the Prescaler divides the VPOB clock PCLK to yield the prescaler clock that is, in turn, divided by the SCR factor in SSPCR0, to determine the bit clock. Table 121: SSP Clock Prescale Register (SSPCPSR - 0xE0068010) SSPCPSR Name Description 7:0 CPSDVSR This even value between 2 and 254, by which PCLK is divided to yield the prescaleroutput clock. Bit 0 always reads as 0. SSP Interrupt Mask Set/Clear Register (SSPIMSC - 0xE0068014) Reset Value This register controls whether each of the four possible interrupt conditions in the SSP controller are enabled. Note that ARM uses the word “masked” in the opposite sense from classic computer terminology, in which “masked” meant “disabled”. ARM uses the word “masked” to mean “enabled”. To avoid confusion we will not use the word “masked”. Table 122: SSP Interrupt Mask Set/Clear Register (SSPIMSC - 0xE0068014) Reset Value SSPIMSC Name Description Reset Value 3 TXIM Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. 0 2 RXIM Software should set this bit to enable interrupt when the Rx FIFO is at least half full. 0 1 RTIM 0 RORIM Software should set this bit to enable interrupt when a Receive Timeout condition occurs. A Receive Timeout occurs when the Rx FIFO is not empty, and no new data has been received, nor has data been read from the FIFO, for 32 bit times. Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. SSP Controller (SPI1) 173 November 22, 2004 0 0 0
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