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Philips Semiconductors Preliminary User Manual ARM-based Microcontroller SSP Raw Interrupt Status Register (SSPRIS - 0xE0068018) LPC2131/2132/2138 This read-only register contains a 1 for each interrupt condition that is asserted, regardless of whether or not the interrupt is enabled in the SSPIMSC. Table 123: SSP Raw Interrupt Status Register (SSPRIS - 0xE0068018) SSPRIS Name Description Reset Value 3 TXRIS This bit is 1 if the Tx FIFO is at least half empty. 1 2 RXRIS This bit is 1 if the Rx FIFO is at least half full. 0 1 RTRIS 0 RORRIS This bit is 1 if when there is a Receive Timeout condition. Note that a Receive Timeout can be negated if further data is received. This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. SSP Masked Interrupt Status Register (SSPMIS - 0xE006801C) This read-only register contains a 1 for each interrupt condition that is asserted and enabled in the SSPIMSC. When an SSP interrupt occurs, the interrupt service routine should read this register to determine the cause(s) of the interrupt. Table 124: SSP Masked Interrupt Status Register (SSPMIS - 0xE006801C) SSPMIS Name Description Reset Value 3 TXMIS This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. 0 2 RXMIS This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. 0 1 RTMIS 0 RORMIS This bit is 1 when there is a Receive Timeout condition and this interrupt is enabled. Note that a Receive Timeout can be negated if further data is received. This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled. SSP Interrupt Clear Register (SSPICR - 0xE0068020) Software can write one or more one(s) to this write-only register, to clear the corresponding interrupt condition(s) in the SSP controller. Note that the other two interrupt conditions can be cleared by writing or reading the appropriate FIFO, or disabled by clearing the corresponding bit in SSPIMSC. Table 125: SSP Interrupt Clear Register (SSPICR - 0xE0068020) SSPICR Name Description Reset Value 1 RTIC Writing a 1 to this bit clears the Receive Timeout interrupt. NA 0 RORIC Writing a 1 to this bit clears the “frame was received when RxFIFO was full” interrupt. NA SSP Controller (SPI1) 174 November 22, 2004 0 0 0 0
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller 14. TIMER/COUNTER0 AND TIMER/COUNTER1 Timer/Counter0 and Timer/Counter1 are functionally identical except for the peripheral base address. FEATURES LPC2131/2132/2138 A 32-bit Timer/Counter with a programmable 32-bit Prescaler. Counter or Timer operation. Up to four 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. Four 32-bit match registers that allow: - Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation. Up to four external outputs corresponding to match registers, with the following capabilities: - Set low on match. - Set high on match. - Toggle on match. - Do nothing on match. APPLICATIONS Interval Timer for counting internal events. Pulse Width Demodulator via Capture inputs. Free running timer. Timer/Counter0 and Timer/Counter1 175 November 22, 2004
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