LPC2131/2132/2138 User Manual - mct.net

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Philips Semiconductors Preliminary User Manual ARM-based Microcontroller the CLK signal is forced LOW SSEL is forced HIGH the transmit MOSI/MISO pad is in high impedance LPC2131/2132/2138 If the SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSEL master signal being driven LOW. This causes slave data to be enabled onto the MISO input line of the master. Master’s MOSI is enabled. One half SCK period later, valid master data is transferred to the MOSI pin. Now that both the master and slave data have been set, the SCK master clock pin goes HIGH after one further half SCK period. The data is now captured on the rising and propagated on the falling edges of the SCK signal. In the case of a single word transmission, after all bits of the data word have been transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSEL signal must be pulsed HIGH between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSEL pin is returned to its idle state one SCK period after the last bit has been captured. SPI Format with CPOL=0,CPHA=1 The transfer signal sequence for SPI format with CPOL=0, CPHA=1 is shown in Figure 40, which covers both single and continuous transfers. SCK SSEL In this configuration, during idle periods: MOSI MSB MISO Q MSB the SCK signal is forced LOW SSEL is forced HIGH the transmitting MOSI/MISO pin is in high impedance ~ ~ ~ ~ ~ ~ 4 to 16 bits a) Motorola SPI frame format (single transfer) with CPOL=0 and CPHA=1 Figure 40: SPI frame format with CPOL=0 and CPHA=1 SSP Controller (SPI1) 166 November 22, 2004 LSB LSB Q
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2131/2132/2138 If the SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSEL master signal being driven LOW. Master’s MOSI pin is enabled. After a further one half SCK period, both master and slave valid data is enabled onto their respective transmission lines. At the same time, the SCK is enabled with a rising edge transition. Data is then captured on the falling edges and propagated on the rising edges of the SCK signal. In the case of a single word transfer, after all bits have been transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured. For continuous back-to-back transfers, the SSEL pin is held LOW between successive data words and termination is the same as that of the single word transfer. SPI Format with CPOL=1,CPHA=0 Single and continuous transmission signal sequences for SPI format with CPOL=1, CPHA=0 are shown in Figure 41. SCK SSEL SCK SSEL Figure 41: SPI frame format with CPOL=1 and CPHA=0 (a) single and b) continuous transfer) In this configuration, during idle periods MOSI MSB MISO MSB a) Motorola SPI frame format (single transfer) with CPOL=1 and CPHA=0 b) Motorola SPI frame format (continuous transfer) with CPOL=1 and CPHA=0 the SCK signal is forced HIGH SSEL is forced HIGH the transmitting pin MOSI/MISO is in high impedance 4 to 16 bits MOSI MSB LSB MSB MISO MSB LSB 4 to 16 bits ~ ~ ~ ~ ~ ~ If the SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSEL master signal being driven LOW, which causes slave data to be immediately transferred onto the MISO line of the master. Master’s MOSI pin is enabled. SSP Controller (SPI1) 167 November 22, 2004 ~ ~ ~ ~ ~ ~ LSB LSB Q Q MSB LSB Q 4 to 16 bits ~ ~ ~ ~ ~ ~ LSB
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