LPC2131/2132/2138 User Manual - mct.net

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Philips Semiconductors Preliminary User Manual ARM-based Microcontroller Table 71: UART0 Line Status Register (U0LSR - 0xE000C014, Read Only) U0LSR Function Description 0 1 2 3 4 5 6 7 Receiver Data Ready (RDR) Overrun Error (OE) Parity Error (PE) Framing Error (FE) Break Interrupt (BI) Transmitter Holding Register Empty (THRE) Transmitter Empty (TEMT) Error in Rx FIFO (RXFE) 0: U0RBR is empty 1: U0RBR contains valid data U0LSR0 is set when the U0RBR holds an unread character and is cleared when the UART0 RBR FIFO is empty. LPC2131/2132/2138 0: Overrun error status is inactive. 1: Overrun error status is active. The overrun error condition is set as soon as it occurs. An U0LSR read clears U0LSR1. U0LSR1 is set when UART0 RSR has a new character assembled and the UART0 RBR FIFO is full. In this case, the UART0 RBR FIFO will not be overwritten and the character in the UART0 RSR will be lost. 0: Parity error status is inactive. 1: Parity error status is active. When the parity bit of a received character is in the wrong state, a parity error occurs. An U0LSR read clears U0LSR2. Time of parity error detection is dependent on U0FCR0. A parity error is associated with the character at the top of the UART0 RBR FIFO. 0: Framing error status is inactive. 1: Framing error status is active. When the stop bit of a received character is a logic 0, a framing error occurs. An U0LSR read clears U0LSR3. The time of the framing error detection is dependent on U0FCR0. A framing error is associated with the character at the top of the UART0 RBR FIFO. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. 0: Break interrupt status is inactive. 1: Break interrupt status is active. When RxD0 is held in the spacing state (all 0’s) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RxD0 goes to marking state (all 1’s). An U0LSR read clears this status bit. The time of break detection is dependent on U0FCR0. The break interrupt is associated with the character at the top of the UART0 RBR FIFO. 0: U0THR contains valid data. 1: U0THR is empty. THRE is set immediately upon detection of an empty UART0 THR and is cleared on a U0THR write. 0: U0THR and/or the U0TSR contains valid data. 1: U0THR and the U0TSR are empty. TEMT is set when both U0THR and U0TSR are empty; TEMT is cleared when either the U0TSR or the U0THR contain valid data. 0: U0RBR contains no UART0 Rx errors or U0FCR0=0. 1: UART0 RBR contains at least one UART0 Rx error. U0LSR7 is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the U0RBR. This bit is cleared when the U0LSR register is read and there are no subsequent errors in the UART0 FIFO. Reset Value UART0 96 November 22, 2004 0 0 0 0 0 1 1 0
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller UART0 Scratch Pad Register (U0SCR - 0xE000C01C) LPC2131/2132/2138 The U0SCR has no effect on the UART0 operation. This register can be written and/or read at user’s discretion. There is no provision in the interrupt interface that would indicate to the host that a read or write of the U0SCR has occurred. Table 72: UART0 Scratch Pad Register (U0SCR - 0xE000C01C) U0SCR Function Description 7:0 - A readable, writable byte. 0 UART0 Baudrate Calculation Example 1: Using UART0 baudrate formula from above, it can be determined that system with pclk=20 MHz, U0DL=130 (U0DLM=0x00 and U0DLL=0x82), DivAddVal=0 and MulVal=1 will enable UART0 with UART0 baudrate =9615 bauds. Example 2: Using UART0 baudrate formula from above, it can be determined that system with pclk=20 MHz, U0DL=93 (U0DLM=0x00 and U0DLL=0x5D), DivAddVal=2 and MulVal=5 will enable UART0 with UART0 baudrate =9600 bauds. Table 73: Baud-rates using 20 MHz peripheral clock (pclk) Desired baud-rate U0DLM:U0DLL 1) % error 2) Desired baud-rate UART0 Transmit Enable Register (U0TER - 0xE0010030) Reset Value U0DLM:U0DLL 1) % error 2) 50 25000 0.0000 4800 260 0.1600 75 16667 0.0020 7200 174 0.2240 110 11364 0.0032 9600 130 0.1600 134.5 9294 0.0034 19200 65 0.1600 150 8333 0.0040 38400 33 1.3760 300 4167 0.0080 56000 22 1.4400 600 2083 0.0160 57600 22 1.3760 1200 1042 0.0320 112000 11 1.4400 1800 694 0.0640 115200 11 1.3760 2000 625 0.0000 224000 6 7.5200 2400 521 0.0320 448000 3 7.5200 3600 347 0.0640 1) values in the row represent decimal equivalent of a 16-bit long content {DLM:DLL} 2) refers to the percent error between desired and actual baud-rate LPC2132/2138’s U0TER enables implementation of software flow control. When TxEn=1, UART0 transmitter will keep sending data as long as they are available. As soon as TxEn becomes 0, UART0 transmittion will stop. UART0 97 November 22, 2004
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