LPC2131/2132/2138 User Manual - mct.net

Philips Semiconductors Preliminary User Manual
ARM-based Microcontroller
Table 24: Power Control for Peripherals Register for LPC2131/2132/2138 (PCONP - 0xE01FC0C4)
PCONP Function Description
Power Control Usage Notes
LPC2131/2132/2138
7 PCI2C0 When 1, the I 2 C0 interface is enabled. When 0, the I 2 C0 interface is disabled to conserve power. 1
8 PCSPI0 When 1, the SPI0 interface is enabled. When 0, the SPI0 is disabled to conserve power. 1
9 PCRTC When 1, the RTC is enabled. When 0, the RTC is disabled to conserve power. 1
10 PCSPI1 When 1, the SSP interface is enabled. When 0, the SSP is disabled to conserve power. 1
11 Reserved User software should write 0 here to reduce power consumption. 1
12 PCAD0
After every reset, PCONP register contains the value that enables all interfaces and peripherals controlled by the PCONP to be
enabled. Therefore, apart from proper configuring via peripheral dedicated registers, user’s application has no need to access
the PCONP in order to start using any of the on-board peripherals.
Power saving oriented systems should have 1s in the PCONP register only in positions that match peripherals really used in the
application. All other bits, declared to be "Reserved" or dedicated to the peripherals not used in the current application, must be
cleared to 0.
RESET
When 1, A/D converter 0 is enabled. When 0, A/D 0 is disabled to conserve power. Clear the
PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN.
18:13 Reserved
Reserved, user software should not write ones to reserved bits. The value read from a reserved
bit is not defined.
0
19 PCI2C1 When 1, the I 2 C1 interface is enabled. When 0, the I 2 C1 interface is disabled to conserve power. 1
20 PCAD1
31:21 Reserved
When 1, A/D converter 1 is enabled. When 0, A/D 1 is disabled to conserve power. Clear the
PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN.
Reserved, user software should not write ones to reserved bits. The value read from a reserved
bit is not defined.
Reset
Value
Reset has two sources on the LPC2131/2132/2138: the RESET pin and Watchdog Reset. The RESET pin is a Schmitt trigger
input pin with an additional glitch filter. Assertion of chip Reset by any source starts the Wakeup Timer (see Wakeup Timer
description later in this chapter), causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running,
a fixed number of clocks have passed, and the on-chip circuitry has completed its initialization. The relationship between Reset,
the oscillator, and the Wakeup Timer are shown in Figure 11.
The Reset glitch filter allows the processor to ignore external reset pulses that are very short, and also determines the minimum
duration of RESET that must be asserted in order to guarantee a chip reset. Once asserted, RESET pin can be deasserted only
when crystal oscillator is fully running and an adequate signal is present on the X1 pin of the LPC2131/2132/2138. Assuming that
an external crystal is used in the crystal oscillator subsystem, after power on, the RESET pin should be asserted for 10 ms. For
all subsequent resets when crystal oscillator is already running and stable signal is on the X1 pin, the RESET pin needs to be
asserted for 300 ns only.
When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from
the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.
System Control Block 47 November 22, 2004
1
1
0