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Philips Semiconductors Preliminary User Manual ARM-based Microcontroller SK CS SO SI LSB 0 ~ ~ ~ ~ ~ MSB LSB ~ 4 to 16 bits output data MSB LSB 8-bit control Figure 44: Microwire frame format (continuos transfers) Setup and hold time requirements on CS with respect to SK in Microwire mode LPC2131/2132/2138 In the Microwire mode, the SSP slave samples the first bit of receive data on the rising edge of SK after CS has gone LOW. Masters that drive a free-running SK must ensure that the CS signal has sufficient setup and hold margins with respect to the rising edge of SK. Figure 45 illustrates these setup and hold time requirements. With respect to the SK rising edge on which the first bit of receive data is to be sampled by the SSP slave, CS must have a setup of at least two times the period of SK on which the SSP operates. With respect to the SK rising edge previous to this edge, CS must have a hold of at least one SK period. SK CS SI t HOLD =t SK t SETUP =2*t SK Figure 45: Microwire frame format (continuos transfers) MSB LSB 4 to 16 bits output data SSP Controller (SPI1) 170 November 22, 2004 ~ ~ ~ ~ ~ ~
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller REGISTER DESCRIPTIONS LPC2131/2132/2138 The base address of the SSP controller is 0xE006 8000. Its registers’ offsets from this base are shown in the following table. Table 116: SSP Registers Name Description Access Address SSPCR0 Control Register 0. Selects the serial clock rate, bus type, and data size. Read/Write 0xE0068000 SSPCR1 Control Register 1. Selects master/slave and other modes. Read/Write 0xE0068004 SSPDR Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. Read/Write 0xE0068008 SSPSR Status Register. Read Only 0xE006800C SSPCPSR Clock Prescale Register. Read/Write 0xE0068010 SSPIMSC Interrupt Mask Set and Clear Register Read/Write 0xE0068014 SSPRIS Raw Interrupt Status Register. Read/Write 0xE0068018 SSPMIS Masked Interrupt Status Register Read/Write 0xE006801C SSPICR Interrupt Clear Register Read/Write 0xE0068020 SSP Control Register 0 (SSPCR0 - 0xE0068000) This register controls the basic operation of the SSP controller. Table 117: SSP Control Register 0 (SSPCR0 - 0xE0068000) SSPCR0 Name Description 15:8 SCR 7 CPHA 6 CPOL Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVR is the prescale divider, and the VPB clock PCLK clocks the prescaler, the bit frequency is f(PCLK) / (CPSDVSR * (SCR+1)). Clock Out Phase. This bit is only used in SPI mode. If it is 0, the SSP controller maintains the bus clock low between frames, while if its 1, the SSP controller maintains the bus clock high between frames Clock Out Polarity. This bit is only used in SPI mode. If it is 0, the SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line. If this bit is 1, the SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line. 5:4 FRF Frame Format. 00 = SPI, 01 = SSI, 10 = Microwire, 11 = reserved. 0 3:0 DSS Data Size Select. This field controls the number of bits transferred in each frame: 0000-0010=reserved, 0011=4 bits, ..., 0111=8 bits, ..., 1111=16 bits. Reset Value SSP Controller (SPI1) 171 November 22, 2004 0 0 0 0
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