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Philips Semiconductors Preliminary User Manual ARM-based Microcontroller I2STAT = 00H: LPC2131/2132/2138 This status code indicates that a bus error has occurred during an I 2 C serial transfer. A bus error is caused when a START or STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. A bus error may also be caused when external interference disturbs the internal I 2 C block signals. When a bus error occurs, SI is set. To recover from a bus error, the STO flag must be set and SI must be cleared. This causes the I 2 C block to enter the “not addressed” slave mode (a defined state) and to clear the STO flag (no other bits in I2CON are affected). The SDA and SCL lines are released (a STOP condition is not transmitted). Table 106: Miscellaneous States STATUS STATUS OF THE I CODE (I2STAT) 2 C BUS AND HARDWARE F8H No relevant state information available; SI = 0 00H Bus error during MST or selected slave modes, due to an illegal START or STOP condition. State 00H can also occur when interference causes the I 2 C block to enter an undefined state. Some Special Cases: The I 2 C hardware has facilities to handle the following special cases that may occur during a serial transfer: Simultaneous Repeated START Conditions from Two Masters A repeated START condition may be generated in the master transmitter or master receiver modes. A special case occurs if another master simultaneously generates a repeated START condition (see Figure 33). Until this occurs, arbitration is not lost by either master since they were both transmitting the same data. If the I 2 C hardware detects a repeated START condition on the I 2 C bus before generating a repeated START condition itself, it will release the bus, and no interrupt request is generated. If another master frees the bus by generating a STOP condition, the I 2 C block will transmit a normal START condition (state 08H), and a retry of the total serial data transfer can commence. Data Transfer After Loss of Arbitration Arbitration may be lost in the master transmitter and master receiver modes (see Figure 27). Loss of arbitration is indicated by the following states in I2STAT; 38H, 68H, 78H, and B0H (see Figures 29 and 30). If the STA flag in I2CON is set by the routines which service these states, then, if the bus is free again, a START condition (state 08H) is transmitted without intervention by the CPU, and a retry of the total serial transfer can commence. Forced Access to the I 2 C Bus APPLICATION SOFTWARE RESPONSE TO/FROM I2DAT TO I2CON STA STO SI AA NEXT ACTION TAKEN BY I 2 C HARDWARE No I2DAT action No I2CON action Wait or proceed current transfer No I2DAT action 0 1 0 X Only the internal hardware is affected in the MST or addressed SLV modes. In all cases, the bus is released and the I 2 C block is switched to the not addressed SLV mode. STO is reset. In some applications, it may be possible for an uncontrolled source to cause a bus hang-up. In such situations, the problem may be caused by interference, temporary interruption of the bus or a temporary short-circuit between SDA and SCL. I2C Interfaces I2C0 and I2C1 140 November 22, 2004
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2131/2132/2138 If an uncontrolled source generates a superfluous START or masks a STOP condition, then the I 2 C bus stays busy indefinitely. If the STA flag is set and bus access is not obtained within a reasonable amount of time, then a forced access to the I 2 C bus is possible. This is achieved by setting the STO flag while the STA flag is still set. No STOP condition is transmitted. The I 2 C hardware behaves as if a STOP condition was received and is able to transmit a START condition. The STO flag is cleared by hardware (see Figure 34). I 2 C Bus Obstructed by a Low Level on SCL or SDA An I 2 C bus hang-up occurs if SDA or SCL is pulled LOW by an uncontrolled source. If the SCL line is obstructed (pulled LOW) by a device on the bus, no further serial transfer is possible, and the I 2 C hardware cannot resolve this type of problem. When this occurs, the problem must be resolved by the device that is pulling the SCL bus line LOW. If the SDA line is obstructed by another device on the bus (e.g., a slave device out of bit synchronization), the problem can be solved by transmitting additional clock pulses on the SCL line (see Figure 35). The I 2 C hardware transmits additional clock pulses when the STA flag is set, but no START condition can be generated because the SDA line is pulled LOW while the I 2 C bus is considered free. The I 2 C hardware attempts to generate a START condition after every two additional clock pulses on the SCL line. When the SDA line is eventually released, a normal START condition is transmitted, state 08H is entered, and the serial transfer continues. If a forced bus access occurs or a repeated START condition is transmitted while SDA is obstructed (pulled LOW), the I 2 C hardware performs the same action as described above. In each case, state 08H is entered after a successful START condition is transmitted and normal serial transfer continues. Note that the CPU is not involved in solving these bus hang-up problems. Bus Error A bus error occurs when a START or STOP condition is present at an illegal position in the format frame. Examples of illegal positions are during the serial transfer of an address byte, a data bit, or an acknowledge bit. The I 2 C hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave. When a bus error is detected, the I 2 C block immediately switches to the not addressed slave mode, releases the SDA and SCL lines, sets the interrupt flag, and loads the status register with 00H. This status code may be used to vector to a state service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in Table 106. S SLA W A Data A 08H 18H 28H S Other Master continues P S SLA Other Master sends Repeated Start earlier Figure 33: Simultaneous Repeated START Conditions from 2 Masters I2C Interfaces I2C0 and I2C1 141 November 22, 2004 08H Retry
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