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Philips Semiconductors Preliminary User Manual ARM-based Microcontroller Table 201: ETM Configuration External Outputs 0 1. For details refer to ARM documentation "Embedded Trace Macrocell Specification (ARM IHI 0014E)". PIN DESCRIPTION RESET STATE OF MULTIPLEXED PINS LPC2131/2132/2138 FIFOFULL Present Yes (Not wired) FIFO depth 10 bytes Trace Packet Width 4/8 Table 202: ETM Pin Description Pin Name Type Description TRACECLK Output PIPESTAT[2:0] Output TRACESYNC Output TRACEPKT[3:0] Output Resource number/type Small 1 EXTIN[0] Input External Trigger Input. Trace Clock. The trace clock signal provides the clock for the trace port. PIPESTAT[2:0], TRACESYNC, and TRACEPKT[3:0] signals are referenced to the rising edge of the trace clock. This clock is not generated by the ETM block. It is to be derived from the system clock. The clock should be balanced to provide sufficient hold time for the trace data signals. Half rate clocking mode is supported. Trace data signals should be shifted by a clock phase from TRACECLK. Refer to Figure 3.14 page 3.26 and figure 3.15 page 3.27 in "ETM7 Technical Reference Manual" (ARM DDI 0158B), for example circuits that implements both half-rateclocking and shifting of the trace data with respect to the clock. For TRACECLK timings refer to section 5.2 on page 5-13 in "Embedded Trace Macrocell Specification" (ARM IHI 0014E). Pipe Line status. The pipeline status signals provide a cycle-by-cycle indication of what is happening in the execution stage of the processor pipeline. Trace synchronization. The trace sync signal is used to indicate the first packet of a group of trace packets and is asserted HIGH only for the first packet of any branch address. Trace Packet. The trace packet signals are used to output packaged address and data information related to the pipeline status. All packets are eight bits in length. A packet is output over two cycles. In the first cycle, Packet[3:0] is output and in the second cycle, Packet[7:4] is output. On the LPC2131/2132/2138, the ETM pin functions are multiplexed with P1.25-16. To have these pins come as a Trace port, connect a weak bias resistor (4.7 k:) between the P1.20/TRACESYNC pin and V SS . To have them come up as port pins, do not connect a bias resistor to P1.20/TRACESYNC, and ensure that any external driver connected to P1.20/TRACESYNC is either driving high, or is in high-impedance state, during Reset. Embedded Trace Macrocell 250 November 22, 2004
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller REGISTER DESCRIPTION LPC2131/2132/2138 The ETM contains 29 registers as shown in Table 203. below. They are described in detail in the ARM IHI 0014E document published by ARM Limited, which is available via the Internet at http://www.arm.com. Table 203: ETM Registers Name Description Access Register encoding ETM Control Controls the general operation of the ETM Read/Write 000 0000 ETM Configuration Code Allows a debugger to read the number of each type of resource Read Only 000 0001 Trigger Event Holds the controlling event Write Only 000 0010 Eight-bit register, used to statically configure the memory map Memory Map Decode Control decoder Write Only 000 0011 ETM Status Holds the pending overflow status bit Read Only 000 0100 System Configuration Holds the configuration information using the SYSOPT bus Read Only 000 0101 Trace Enable Control 3 Holds the trace on/off addresses Write Only 000 0110 Trace Enable Control 2 Holds the address of the comparison Write Only 000 0111 Trace Enable Event Holds the enabling event Write Only 000 1000 Trace Enable Control 1 Holds the include and exclude regions Write Only 000 1001 FIFOFULL Region Holds the include and exclude regions Write Only 000 1010 FIFOFULL Level Holds the level below which the FIFO is considered full Write Only 000 1011 ViewData event Holds the enabling event Write Only 000 1100 ViewData Control 1 Holds the include/exclude regions Write Only 000 1101 ViewData Control 2 Holds the include/exclude regions Write Only 000 1110 ViewData Control 3 Holds the include/exclude regions Write Only 000 1111 Address Comparator 1 to 16 Holds the address of the comparison Write Only 001 xxxx Address Access Type 1 to 16 Holds the type of access and the size Write Only 010 xxxx reserved - - 000 xxxx reserved - - 100 xxxx Initial Counter Value 1 to 4 Holds the initial value of the counter Write Only 101 00xx Counter Enable 1 to 4 Holds the counter clock enable control and event Write Only 101 01xx Counter reload 1 to 4 Holds the counter reload event Write Only 101 10xx Counter Value 1 to 4 Holds the current counter value Read Only 101 11xx Sequencer State and Control Holds the next state triggering events. - 110 00xx External Output 1 to 4 Holds the controlling events for each output Write Only 110 10xx Reserved - - 110 11xx Reserved - - 111 0xxx Reserved - - 111 1xxx Embedded Trace Macrocell 251 November 22, 2004
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