LPC2131/2132/2138 User Manual - mct.net

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Philips Semiconductors Preliminary User Manual ARM-based Microcontroller System Control Block (VPB peripheral #127) (VPB peripherals #28-126) not used DAC (VPB peripheral #27) SSP (VPB peripheral #26) not used (VPB peripheral #25) 10 bit AD1 (LPC2138) (VPB peripheral #24) I not used (VPB peripheral #14-22) 2C1 (VPB peripheral #23) 10 bit AD0 (VPB peripheral #13) not used (VPB peripheral #12) Pin Connect Block (VPB peripheral #11) GPIO (VPB peripheral #10) RTC (VPB peripheral #9) SPI0 (VPB peripheral #8) PWM (VPB peripheral #5) UART1 (VPB peripheral #4) UART0 (VPB peripheral #3) TIMER0 (VPB peripheral #1) Watchdog Timer (VPB peripheral #0) Figure 5: VPB Peripheral Map 0xE01F FFFF 0xE002 0000 I not used (VPB peripheral #6) 2 C0 (VPB peripheral #7) 0xE001 C000 TIMER1 (VPB peripheral #2) 0xE01F C000 0xE007 0000 0xE006 C000 0xE006 8000 0xE006 4000 0xE006 0000 0xE005 C000 0xE003 8000 0xE003 4000 0xE003 0000 0xE002 C000 0xE002 8000 0xE002 4000 0xE001 8000 0xE001 4000 0xE001 0000 0xE000 C000 0xE000 8000 0xE000 4000 0xE000 0000 LPC2131/2132/2138 LPC2131/2132/2138 Memory Addressing 24 November 22, 2004
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2131/2132/2138 MEMORY RE-MAPPING AND BOOT BLOCK Memory Map Concepts and Operating Modes LPC2131/2132/2138 The basic concept on the LPC2131/2132/2138 is that each memory area has a "natural" location in the memory map. This is the address range for which code residing in that area is written. The bulk of each memory space remains permanently fixed in the same location, eliminating the need to have portions of the code designed to run in different address ranges. Because of the location of the interrupt vectors on the ARM7 processor (at addresses 0x0000 0000 through 0x0000 001C, as shown in Table 2 below), a small portion of the Boot Block and SRAM spaces need to be re-mapped in order to allow alternative uses of interrupts in the different operating modes described in Table 3. Re-mapping of the interrupts is accomplished via the Memory Mapping Control feature described in the System Control Block section. Table 2: ARM Exception Vector Locations Address Exception 0x0000 0000 Reset 0x0000 0004 Undefined Instruction 0x0000 0008 Software Interrupt 0x0000 000C Prefetch Abort (instruction fetch memory fault) 0x0000 0010 Data Abort (data access memory fault) 0x0000 0014 Reserved * 0x0000 0018 IRQ 0x0000 001C FIQ *: Identified as reserved in ARM documentation, this location is used by the Boot Loader as the Valid User Program key. This is descibed in detail in Flash Memory System and Programming on page 225. Table 3: LPC2131/2132/2138 Memory Mapping Modes Mode Activation Usage Boot Loader mode User Flash mode User RAM mode Hardware activation by any Reset Software activation by Boot code Software activation by User program The Boot Loader always executes after any reset. The Boot Block interrupt vectors are mapped to the bottom of memory to allow handling exceptions and using interrupts during the Boot Loading process. Activated by Boot Loader when a valid User Program Signature is recognized in memory and Boot Loader operation is not forced. Interrupt vectors are not re-mapped and are found in the bottom of the Flash memory. Activated by a User Program as desired. Interrupt vectors are re-mapped to the bottom of the Static RAM. LPC2131/2132/2138 Memory Addressing 25 November 22, 2004
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LPC2131/2132/2138 User Manual - mct.net

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