LPC2131/2132/2138 User Manual - mct.net

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Philips Semiconductors Preliminary User Manual ARM-based Microcontroller Memory Re-Mapping LPC2131/2132/2138 In order to allow for compatibility with future derivatives, the entire Boot Block is mapped to the top of the on-chip memory space. In this manner, the use of larger or smaller flash modules will not require changing the location of the Boot Block (which would require changing the Boot Loader code itself) or changing the mapping of the Boot Block interrupt vectors. Memory spaces other than the interrupt vectors remain in fixed locations. Figure 6 shows the on-chip memory mapping in the modes defined above. The portion of memory that is re-mapped to allow interrupt processing in different modes includes the interrupt vector area (32 bytes) and an additional 32 bytes, for a total of 64 bytes. The re-mapped code locations overlay addresses 0x0000 0000 through 0x0000 003F. A typical user program in the Flash memory can place the entire FIQ handler at address 0x0000 001C without any need to consider memory boundaries. The vector contained in the SRAM, external memory, and Boot Block must contain branches to the actual interrupt handlers, or to other instructions that accomplish the branch to the interrupt handlers. There are three reasons this configuration was chosen: 1. To give the FIQ handler in the Flash memory the advantage of not having to take a memory boundary caused by the remapping into account. 2. Minimize the need to for the SRAM and Boot Block vectors to deal with arbitrary boundaries in the middle of code space. 3. To provide space to store constants for jumping beyond the range of single word branch instructions. Re-mapped memory areas, including the Boot Block and interrupt vectors, continue to appear in their original location in addition to the re-mapped address. Details on re-mapping and examples can be found in System Control Block on page 29. LPC2131/2132/2138 Memory Addressing 26 November 22, 2004
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller 2.0 GB 2.0 GB - 8K 1.0 GB 0.0 GB Note: memory regions are not drawn to scale. 12K byte Boot Block (re-mapped from top of Flash memory) (Boot Block interrupt vectors) Reserved Addressing Space 32 kB On-Chip SRAM (SRAM interrupt vectors) Reserved Addressing Space (12k byte Boot Block re-Mapped to higher address range) 512K byte Flash Memory Active interrupt vectors (from Flash, SRAM, or Boot Block) 0x8000 0000 0x7FFF FFFF 0x4000 8000 0x4000 7FFF 0x4000 0000 0x3FFF FFFF 0x0008 0000 0x0007 FFFF 0x0000 0000 LPC2131/2132/2138 Figure 6: Map of lower memory is showing re-mapped and re-mappable areas (LPC2138 with 512 kB Flash). LPC2131/2132/2138 Memory Addressing 27 November 22, 2004
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