LPC2131/2132/2138 User Manual - mct.net

Philips Semiconductors Preliminary User Manual
ARM-based Microcontroller
LPC2131/2132/2138
asserting the ARM7TDMI-S local bus signal CLKEN.) Under some conditions, this delay could result in a Watchdog time-out. The
user will need to be aware of this possibility and take steps to insure that an unwanted Watchdog reset does not cause a system
failure while programming or erasing the Flash memory.
In order to preclude the possibility of stale data being read from the Flash memory, the LPC2131/2132/2138 MAM holding latches
are automatically invalidated at the beginning of any Flash programming or erase operation. Any subsequent read from a Flash
address will cause a new fetch to be initiated after the Flash operation has completed.
MEMORY ACCELERATOR MODULE OPERATING MODES
Three modes of operation are defined for the MAM, trading off performance for ease of predictability:
0) MAM off. All memory requests result in a Flash read operation (see note 2 below). There are no instruction prefetches.
1) MAM partially enabled. Sequential instruction accesses are fulfilled from the holding latches if the data is present. Instruction
prefetch is enabled. Non-sequential instruction accesses initiate Flash read operations (see note 2 below). This means that all
branches cause memory fetches. All data operations cause a Flash read because buffered data access timing is hard to predict
and is very situation dependent.
2) MAM fully enabled. Any memory request (code or data) for a value that is contained in one of the corresponding holding latches
is fulfilled from the latch. Instruction prefetch is enabled. Flash read operations are initiated for instruction prefetch and code or
data values not available in the corresponding holding latches.
Table 28: MAM Responses to Program Accesses of Various Types
MAM Mode
Program Memory Request Type
0 1 2
Sequential access, data in MAM latches Initiate Fetch 2
Use Latched Data 1
Use Latched Data 1
Sequential access, data not in MAM latches Initiate Fetch Initiate Fetch 1
Initiate Fetch 1
Non-Sequential access, data in MAM latches Initiate Fetch 2 Initiate Fetch 1, 2 Use Latched Data 1
Non-Sequential access, data not in MAM latches Initiate Fetch Initiate Fetch 1
Table 29: MAM Responses to Data and DMA Accesses of Various Types
Data Memory Request Type
MAM Mode
Initiate Fetch 1
0 1 2
Sequential access, data in MAM latches Initiate Fetch 2 Initiate Fetch 2 Use Latched Data
Sequential access, data not in MAM latches Initiate Fetch Initiate Fetch Initiate Fetch
Non-Sequential access, data in MAM latches Initiate Fetch 2 Initiate Fetch 2 Use Latched Data
Non-Sequential access, data not in MAM latches Initiate Fetch Initiate Fetch Initiate Fetch
1. Instruction prefetch is enabled in modes 1 and 2.
2. The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This saves power while
resulting in the same execution timing. The MAM can truly be turned off by setting the fetch timing value in MAMTIM to one
clock.
Memory Accelerator Module (MAM) 57 November 22, 2004