LPC2131/2132/2138 User Manual - mct.net

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Philips Semiconductors Preliminary User Manual ARM-based Microcontroller DESCRIPTION LPC2131/2132/2138 The Timer/Counter is designed to count cycles of the peripheral clock (pclk) or an externally-supplied clock, and can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. PIN DESCRIPTION Table 126 gives a brief summary of each of the Timer related pins. Table 126: Pin summary Pin name Pin direction Pin Description CAP0.3..0 CAP1.3..0 MAT0.3...0 MAT1.0...0 Input Output Capture Signals- A transition on a capture pin can be configured to load one of the Capture Registers with the value in the Timer Counter and optionally generate an interrupt. Capture functionality can be selected from a number of pins. When more than one pin is selected for a Capture input on a single TIMER0/1 channel, the pin with the lowest Port number is used. If for example pins 30 (P0.6) and 46 (P0.16) are selected for CAP0.2, only pin 30 will be used by TIMER0 to perform CAP0.2 function. Here is the list of all CAPTURE signals, together with pins on where they can be selected: CAP0.0 (3 pins) : P0.2, P0.22 and P0.30 CAP0.1 (2 pins) : P0.4 and P0.27 CAP0.2 (3 pin) : P0.6, P0.16 and P0.28 CAP0.3 (1 pin): : P0.29 CAP1.0 (1 pin): : P0.10 CAP1.1 (1 pin): : P0.11 CAP1.2 (2 pins) : P0.17 and P0.19 CAP1.3 (2 pins) : P0.18 and P0.21 Timer/Counter block can select a capture signal as a clock source instead of the pclk derived clock. For more details see Count Control Register (CTCR: TIMER0 - T0CTCR: 0xE0004070; TIMER1 - T1TCR: 0xE0008070) on page 178 External Match Output 0/1- When a match register 0/1 (MR3:0) equals the timer counter (TC) this output can either toggle, go low, go high, or do nothing. The External Match Register (EMR) controls the functionality of this output. Match Output functionality can be selected on a number of pins in parallel. It is also possible for example, to have 2 pins selected at the same time so that they provide MAT1.3 function in parallel. Here is the list of all MATCH signals, together with pins on where they can be selected: MAT0.0 (2 pins) : P0.3 and P0.22 MAT0.1 (2 pins) : P0.5 and P0.27 MAT0.2 (2 pin) : P0.16 and P0.28 MAT0.3 (1 pin): : P0.29 MAT1.0 (1 pin): : P0.12 MAT1.1 (1 pin): : P0.13 MAT1.2 (2 pins) : P0.17 and P0.19 MAT1.3 (2 pins) : P0.18 and P0.20 Timer/Counter0 and Timer/Counter1 176 November 22, 2004
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller REGISTER DESCRIPTION LPC2131/2132/2138 Each Timer contains the registers shown in Table 127 ("Reset Value" refers to the data stored in used bits only; it does not include reserved bits content). More detailed descriptions follow. Table 127: TIMER0 and TIMER1 Register Map Generic Name IR TCR TC PR PC MCR MR0 Description Access Reset Value* Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. Timer Counter. The 32-bit TC is incremented every PR+1 cycles of pclk. The TC is controlled through the TCR. Prescale Register. The TC is incremented every PR+1 cycles of pclk. Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented. Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. R/W 0 R/W 0 RW 0 R/W 0 R/W 0 R/W 0 R/W 0 MR1 Match Register 1. See MR0 description. R/W 0 MR2 Match Register 2. See MR0 description. R/W 0 MR3 Match Register 3. See MR0 description. R/W 0 CCR CR0 Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAP0.0(CAP1.0) input. R/W 0 RO 0 CR1 Capture Register 1. See CR0 description. RO 0 CR2 Capture Register 2. See CR0 description. RO 0 CR3 Capture Register 3. See CR0 description. RO 0 EMR CTCR External Match Register. The EMR controls the external match pins MAT0.0-3 (MAT1.0-3). Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. R/W 0 R/W 0 TIMER0 Address & Name 0xE0004000 T0IR 0xE0004004 T0TCR 0xE0004008 T0TC 0xE000400C T0PR 0xE0004010 T0PC 0xE0004014 T0MCR 0xE0004018 T0MR0 0xE000401C T0MR1 0xE0004020 T0MR2 0xE0004024 T0MR3 0xE0004028 T0CCR 0xE000402C T0CR0 0xE0004030 T0CR1 0xE0004034 T0CR2 0xE0004038 T0CR3 0xE000403C T0EMR 0xE0004070 T0CTCR TIMER1 Address & Name 0xE0008000 T1IR 0xE0008004 T1TCR 0xE0008008 T1TC 0xE000800C T1PR 0xE0008010 T1PC 0xE0008014 T1MCR 0xE0008018 T1MR0 0xE000801C T1MR1 0xE0008020 T1MR2 0xE0008024 T1MR3 0xE0008028 T1CCR 0xE000802C T1CR0 0xE0008030 T1CR1 0xE0008034 T1CR2 0xE0008038 T1CR3 0xE000803C T1EMR 0xE0008070 T1CTCR Timer/Counter0 and Timer/Counter1 177 November 22, 2004
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