LPC2131/2132/2138 User Manual - mct.net

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Philips Semiconductors Preliminary User Manual ARM-based Microcontroller Table 55: GPIO Register Map Generic Name IOPIN IOSET IODIR IOCLR Description Access GPIO Port Pin value register. The current state of the port pins can always be read from this register, regardless of pin direction and mode. GPIO Port Output set register. This register controls the state of output pins in conjunction with the IOCLR register. Writing ones produces highs at the corresponding port pins. Writing zeroes has no effect. GPIO Port Direction control register. This register individually controls the direction of each port pin. GPIO Port Output clear register. This register controls the state of output pins. Writing ones produces lows at the corresponding port pins and clears the corresponding bits in the IOSET register. Writing zeroes has no effect. Reset Value Read Only NA LPC2131/2132/2138 PORT0 Address & Name 0xE0028000 IO0PIN PORT1 Address & Name 0xE0028010 IO1PIN GPIO 86 November 22, 2004 Read/ Write Read/ Write Write Only 0x0000 0000 0x0000 0000 0x0000 0000 0xE0028004 IO0SET 0xE0028008 IO0DIR 0xE002800C IO0CLR 0xE0028014 IO1SET 0xE0028018 IO1DIR 0xE002801C IO1CLR
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller GPIO Pin Value Register (IO0PIN - 0xE0028000, IO1PIN - 0xE0028010) LPC2131/2132/2138 This register provides the value of the GPIO pins. Register’s value reflects any outside world influence on the GPIO configured pins only. Monitoring of non-GPIO configured port pins using IOPIN register will not be valid, since activities on non-GPIO configured pins are not indicated in the IOPIN register. Selection of a single function on a port pin completely excludes all other functions otherwise available on the same pin. The only partial exception from the above rule of exclusion is in the case of inputs to the A/D converter. Regardless of the function that is selected for the port pin that also hosts the A/D input, this A/D input can be read at any time and variations of the voltage level on this pin will be reflected in the A/D readings. However, valid analog reading(s) can be obtained if and only if the function of an analog input is selected. Only in this case proper interface circuit is active in between the physical pin and the A/D module. In all other cases, a part of digital logic necessary for the digital function to be performed will be active, and will disrupt proper behavior of the A/D. Table 56: GPIO Pin Value Register (IO0PIN - 0xE0028000, IO1PIN - 0xE0028010) IOPIN Description GPIO Output Set Register (IO0SET - 0xE0028004, IO1SET - 0xE0028014) This register is used to produce a HIGH level output at the port pins if they are configured as GPIO in an OUTPUT mode. Writing 1 produces a HIGH level at the corresponding port pins. Writing 0 has no effect. If any pin is configured as an input or a secondary function, writing to IOSET has no effect. Reading the IOSET register returns the value of this register, as determined by previous writes to IOSET and IOCLR (or IOPIN as noted above). This value does not reflect the effect of any outside world influence on the I/O pins. GPIO Output Clear Register (IO0CLR - 0xE002800C, IO1CLR - 0xE002801C) This register is used to produce a LOW level at port pins if they are configured as GPIO in an OUTPUT mode. Writing 1 produces a LOW level at the corresponding port pins and clears the corresponding bits in the IOSET register. Writing 0 has no effect. If any pin is configured as an input or a secondary function, writing to IOCLR has no effect. GPIO Direction Register Value after Reset 31:0 GPIO pin value bits. Bit 0 in IO0PIN corresponds to P0.0 ... Bit 31 in IO0PIN corresponds to P0.31 Undefined Table 57: GPIO Output Set Register (IO0SET - 0xE0028004, IO1SET - 0xE0028014) IOSET Description Value after Reset 31:0 Output value SET bits. Bit 0 in IO0SET corresponds to P0.0 ... Bit 31 in IO0SET corresponds to P0.31 0 Table 58: GPIO Output Clear Register (IO0CLR - 0xE002800C, IO1CLR - 0xE002801C) IOCLR Description 31:0 Output value CLEAR bits. Bit 0 in IO0CLR corresponds to P0.0 ... Bit 31 in IO0CLR corresponds to P0.31 Value after Reset GPIO 87 November 22, 2004 0
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