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Philips Semiconductors Preliminary User Manual ARM-based Microcontroller A/D Data Register (AD0DR - 0xE0034004, AD1DR - 0xE0060004) . Table 146: A/D Data Register (AD0DR - 0xE0034004, AD1DR - 0xE0060004) A/D Global Start Register (ADGSR - 0xE0034008) LPC2131/2132/2138 ADDR Name Description Reset Value 5:0 Reserved Reserved. These bits always read as zeroes. User should not write ones to reserved bits. 0 15:6 V/V 3A When DONE is 1, this field contains a binary fraction representing the voltage on the Ain pin selected by the SEL field, divided by the voltage on the VddA pin. Zero in the field indicates that the voltage on the Ain pin was less than, equal to, or close to that on VSSA , while 0x3FF indicates that the voltage on Ain was close to, equal to, or greater than that on V3A . For testing, data written to this field is captured in a shift register that is clocked by the A/D converter clock. The MS bit of this register sources the DINSERI input of the A/D converter, which is used only when TEST1:0 are 10. 23:16 Reserved Reserved. These bits always read as zeroes. User should not write ones to reserved bits. 0 26:24 CHN These bits contain the channel from which the LS bits were converted. X 29:27 Reserved Reserved. These bits always read as zeroes. User should not write ones to reserved bits. 0 30 OVERUN 31 DONE This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the LS bits. In non-FIFO operation, this bit is cleared by reading this register. This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started. Table 147: A/D Global Start Register (ADGSR - 0xE0034008) ADCR Name Description Reset Value 15:0 Reserved 16 BURST User software should not write ones to reserved bits. The value read from a reserved bit is not defined. If this bit is 0, conversions are software controlled and require 11 clocks. If this bit is 1, the AD converters do repeated conversions at the rate selected by their CLKS fields, scanning (if necessary) through the pins selected by 1s in the SEL fields. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that’s in progress when this bit is cleared will be completed. A/D Converter 200 November 22, 2004 X 0 0 0 0
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller Table 147: A/D Global Start Register (ADGSR - 0xE0034008) OPERATION Hardware-Triggered Conversion LPC2131/2132/2138 ADCR Name Description Reset Value 23:17 Reserved 26:24 START 27 EDGE 31:28 Reserved If the BURST bit in the ADCR is 0 and the START field contains 010-111, the A/D converter will start a conversion when a transition occurs on a selected pin or Timer Match signal. The choices include conversion on a specified edge of any of 4 Match signals, or conversion on a specified edge of either of 2 Capture/Match pins. The pin state from the selected pad or the selected Match signal, XORed with ADCR bit 27, is used in the edge detection logic. Clock Generation It is highly desirable that the clock divider for the 4.5 MHz conversion clock be held in a Reset state when the A/D converter is idle, so that the sampling clock can begin immediately when 01 is written to the START field of the ADCR, or the selected edge occurs on the selected signal. This feature also saves power, particularly if the A/D converter is used infrequently. Interrupts An interrupt request is asserted to the Vectored Interrupt Controller (VIC) when the DONE bit is 1. Software can use the Interrupt Enable bit for the A/D Converter in the VIC to control whether this assertion results in an interrupt. DONE is negated when the ADDR is read. Accuracy vs. Digital Receiver User software should not write ones to reserved bits. The value read from a reserved bit is not defined. When the BURST bit is 0, these bits control whether and when an A/D conversion is started: 000: no start (this value should be used when clearing PDN to 0) 001: start conversion now 010: start conversion when the edge selected by bit 27 occurs on P0.16/EINT0/MAT0.2/ CAP0.2 011: start conversion when the edge selected by bit 27 occurs on P0.22/TD3/CAP0.0/ MAT0.0 Note: for choices 100-111 the MAT signal need not be pinned out: 100: start conversion when the edge selected by bit 27 occurs on MAT0.1 101: start conversion when the edge selected by bit 27 occurs on MAT0.3 110: start conversion when the edge selected by bit 27 occurs on MAT1.0 111: start conversion when the edge selected by bit 27 occurs on MAT1.1 This bit is significant only when the START field contains 010-111. In these cases: 0: start conversion on a falling edge on the selected CAP/MAT signal 1: start conversion on a rising edge on the selected CAP/MAT signal User software should not write ones to reserved bits. The value read from a reserved bit is not defined. While the A/D converter can be used to measure the voltage on any AIN pin, regardless of the pin’s setting in the Pin Select register (Pin Connect Block on page 81), selecting the AIN function improves the conversion accuracy by disabling the pin’s digital receiver. A/D Converter 201 November 22, 2004 0 000 0 0
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