1. xerox 560 computer system - The UK Mirror Service

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3.4.5.If the pattern byte is a field separator (X'22'), the fillcharacter is stored in the pattern byte location. CC1,CC3, and CC4 are all reset to O's, and CC2 remainsunchanged.If the pattern byte is not a digit selector, significancestart, immediate significance start, or field separator,one of the following actions are performed:ConditionsCC1=O }CC4=OCC1=1 }CC4=OCC4=lActionStore fill character in pattern bytelocation.Store blank character (X'40') in patternbyte location.None (pattern byte remains unchanged).Increment the destination address in regi ster Ru 1 anddecrement the count in regi ster Ru 1. If the count issti II nonzero, process the next pattern byte as above;otherwise, execute the next instruction in sequence.R field is an odd value or equal to zero, the instructiontraps to location X'40', instruction exception trap.If an i "egal digit or sign is detected in the decimal informationfield, the basic processor unconditionally abortsexecution of the instruction (at the time the i "egal digitor sign is encountered) and traps to location X'45' with thecontents of register R, register Ru1, register 1, the destinationbyte string, and the condition code containing the resultsof the last editing operation performed before theillegal digit or sign was encountered.See "Traps By Byte-String Instructions llfor other trap conditions.(in this section)In the following examples, the hexadecimal codes for thedigit selector (X' 20'), the significance start (X'21'), thefield separation (X'22'), and the immediate significancestart (X'23') are represented by the character groups ds,ss, fs, and si, respectively. Also, the symbol 1:> is used torepresent the character blank (X'40'). Note that code X'5C'represents the * symbol.Affected: (R),(Ru1)(register 1),(OBS), CCedited (SBS) -OBSTraps: Nonexistentinstruction,decimal arithmetic,instructionexceptionExample 1, before execution:The instruction word isX '63600000'Condition code settings:oo2 3 4 Result of EBS- 0 Significance is not present, no sign digit hasbeen encountered.Signifi cance is present, no sign digit has beenencountered.- 0 A positive sign has been encountered.A negative sign has been encountered.- 0 Next digit to be processed is leftdigitofbyte.Nextdigit to be processed is rightdigitofbyte.- 0 No nonzero digit has been encountered.- A nonzero digit has been encountered.If EBS is indirectly addressed, it is treated as a nonexistentinstruction. The basic processor unconditionally abortsexecution of the instruction (at the time of operation codedecoding) and traps to location X'40' with the contents ofregister R, register Rul, register 1, the destination bytestring, and the condition code unchanged.The R field of the EBS instruction must be an even value(excluding 0) for proper operation of the instruction; if theThe contents of register 6 are:X'5C000100'The contents of register 7 are:X'OCOO1ooo'The contents of the decimal information field beginning atbyte location X'100' are:0000000+The contents of the destination byte string beginning at bytelocation X'lOOO' are:ds ds , ds ds ss . ds ds 1:> C RThe condition code is:0000Example 1, after execution:The instruction word is unchanged.The new contents of register 6 are:X'5C000104'94 Byte-String Instructions
The new contents of register 7 are:X'0000100C'The contents of the decimal information field are unchanged.The new contents of the destination byte string are:******.00'b'b'bThe new condition code is:1000The contents of register 1 are:X'xxx010061By subsequent programming, a floating dollar sign can beinserted in front of the fi rst si gn ifi cant character of theedited byte string by using the contents of register 1,minus 1, as the address of the byte location where thedollar sign is to be inserted.Example 3, after execution:The instruction word and the decimal field are unchanged.The new contents of registers 6 and 7 are identical to thatgiven for example 1.The new contents of the destination byte string are:***543.21'b'b'bThe new condition code is:1010The new contents of register 1 are:X1xxxO 1 003 1Example 4, before execution:The instruction word is:XI 63400 1 00 1The contents of register 4 dre:Example 2, before execution:The initial conditions are identical to example 1, exceptthat the contents of the decimal information field are:065432 1-X'lB001000'The contents of register 5 are:XI 19002000 1Example 2, after execution:Jhe instruction word and the decimal field are unchanged.The new contents of registers 6 and 7 are identical to thosegiven for example 1.The new contents of the destination byte string are:*6,543.21'bCRThe new condition code is:1011The new contents of register 1 are:X' xxx01001 1Example 3, before execution:The initial conditions are identical to example 1, exceptthat the contents of the decimal field are:00 54 32 1+byte location X' l100' are:06 12 50 0+ 01 23 4+ 03 5-The contents of the destination byte stri-ng beginning at bytelocation X' 2000' are: -A ds ds si . ds ds ds fs B ds ds ss . ds ds C fs Dsi ds ds ENDThe condition code is:0100Example 4, after execution:The instruction word is unchanged.The new contents of register 4 are:XI 7BOO 1 009 1The new contents of register 5 are:X'00002019 1The decimal information field is unchanged.Byte-String Instructions 95
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Xerox 560 ComputerReference Manual9
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4. INPUT/OUTPUT OPERA TIO NS 142 AG
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1. XEROX 560 COMPUTER SYSTEMINTRODU
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Many operations are performed in fl
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Rapid Context Switching. When respo
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2. SYSTEM ORGANIZATIONThe elements
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FAST MEMORYARITHMETIC AND CONTROL U
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INFORMATION BOUNDARIESBasic process
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(Maximumof eight)Core Core Core Cor
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3. Diagnostic logic. Each memory dr
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eference address field of the instr
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Instruction in memory:Instruction i
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Real-extended addressing is specifi
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Table 1. Basic Processor Operating
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DesignationFunctionDesignationFunct
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InterruptStateDisarmedArmed[$Waitin
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AddressTable 2. Interrupt Locations
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is assumed to contain an XPSD or a
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Table 3. Summary of Trap LocationsL
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TRAP MASKSThe programmer may mask t
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PUSH-DOWN STACK LIMIT TRAPPush-down
Page 49 and 50: Instruction Name Mnemonic FaultDeci
Page 51 and 52: subroutine. However, with certain c
Page 53 and 54: 3. INSTRUCTION REPERTOIREThis chapt
Page 55 and 56: CC1 is unchanged by the instruction
Page 57 and 58: Condition code settings:2 3 4 Resul
Page 59 and 60: Example 2, odd R field value:Before
Page 61 and 62: significance (FS), floating zero (F
Page 63 and 64: next sequential register after regi
Page 65 and 66: R 1 R2 R3 MeaningoThe effective vir
Page 69 and 70: MIMULTIPLY IMMEDIATE(Immediate oper
Page 71 and 72: original contents of register R, re
Page 73 and 74: Instruction NameCompare HalfwordMne
Page 77 and 78: 2 3 4 Result of ShiftCircular Shift
Page 79 and 80: 4. At the completion of the left sh
Page 81 and 82: Instruction NameFloating Subtract L
Page 83 and 84: The following table shows the possi
Page 85 and 86: Table 8.Condition Code Settings for
Page 87 and 88: PACKED DECIMAL NUMBERSAll decimal a
Page 89 and 90: DSTDECIMAL STORE(Byte index alignme
Page 91 and 92: If no indirect addressing or indexi
Page 93 and 94: Instruction NameMnemonicDesignation
Page 95 and 96: Both byte strings are C bytes in le
Page 97 and 98: of the destination byte that caused
Page 99: again present, unti I a positive or
Page 103 and 104: traps to location X'42 1 as a resul
Page 105 and 106: If there is sufficient space in the
Page 107 and 108: If CC1, or CC3, or both CC1 and CC3
Page 109 and 110: appropriate memory stack locations
Page 111 and 112: II, EI) are generated by II ORing"
Page 113 and 114: In the real extended addressing mod
Page 115 and 116: CAll INSTRUCTIONSEach ofthe four CA
Page 117 and 118: The XPSD instruction' is used for t
Page 119 and 120: If (I)1O = 0, trap or interrupt ins
Page 121 and 122: For either memory map format and ei
Page 123 and 124: initial value plus the initial valu
Page 125 and 126: Table 9. Status Word 0Field Bits Co
Page 127 and 128: READ INTERRUPT INHIBITSThe followin
Page 129 and 130: Table 11.Read Direct Mode 9 Status
Page 131 and 132: SET ALARM INDICATORThe following co
Page 133 and 134: INPUT jOUTPUT INSTRUCTIONSThe I/o i
Page 135 and 136: Table 13.Description of I/o Instruc
Page 137 and 138: Table 15.Device Status Byte (Regist
Page 139 and 140: Table 16. Operational Status Byte (
Page 141 and 142: Table 19.Status Response Bits for A
Page 143 and 144: If CC4 = 0, the MIOP is in a normal
Page 145 and 146: 2 3 4 Meaningo 0 I/o address not re
Page 147 and 148: The functions of bits within the DC
Page 149 and 150: 4. Each unit-record controller (int
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Interrupt at Channel End (Bit Posit
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Transfer in Channel. A control lOCO
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Otherwise, the first word of the ne
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Depending upon the characteristics
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change the rate on the primary cons
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Location(hex) (dec)20 3221 3322 342
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Table 22.Diagnostic Control (P-Mode
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at its normal rate (e. g., fixed du
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SET LOW CLOCK MARGINSThis command c
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BP STATUS AND NO.Th i s group of i
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Input5MPri ntout5MFunctionStore X 1
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6. SYSTEM CONFIGURATION CONTROLPool
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Table 25. Functions of Processor Cl
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Table 26. Functions of Memory Unit
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STANDARD 8-BIT COMPUTER CODES (EBCD
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STANDARD SYMBOL-CODE CORRESPONDENCE
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STANDARD SYMBOL-CODE CORRESPONDENCE
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TABLE OF POWERS OF SIXTEEN II162564
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL FRACTION CONVER
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HEXADECIMAL-DECIMAL FRACTION CONVER
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APPENDIX B.GLOSSARY OF SYMBOLIC TER
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TermMeaningTermMeaningWKxWrite key
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Table C-2. Memory Unit Status Regis
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Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
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