1. xerox 560 computer system - The UK Mirror Service

to as conversion values. The intermediate results of theseinstructions are accumulated in internal basic processorregisters unti I the instruction is completed; the result isthen loaded into the appropriate general register. Bothinstructions use a counter (n) that is set to 0 at the beginningof the instruction execution and is incremented by 1 witheach iteration, until a total of 32 iterations has beenperformed.If a memory parity or protection violation trap occurs duringthe execution of either instruction, the instruction sequenceis aborted (without having changed the contents ofregister R or Rul) and may be restarted (at the beginning ofthe instruction sequence) after the trap routine is processed.eVACONVERT BY ADDITION(yVord index alignment)CONVERT BY ADDITION initially clears the internal A registerand sets an internal counter (n) to O. If bit position nof register Rul contains a 1, CVA adds the nth conversionvalue (contents of the word location pointed to by the effectiveaddress plus n) to the contents of the A register,accumulates the sum in the A register, and increments nby 1. If bit position n of register Ru 1 contains a 0, CVAonly increments n. If n is less than 32 after being incremented,the next bit position of register Rul is examined,and the addition process continues through n equal to 31;the resu It is then loaded into register R. If, on any iteration,the sum has exceeded the value 2 32 - 1, CCl is setto 1 i otherwise, CCl is reset to O.Affected: (R), CC1, CC3, CC4O-A,O-nIf (Rul) =1, then (EWL + n) + (A) -A, n + 1 -nIf (Run =0. then n + 1-n, 'n 'If n < 32, repeat; otherwise, (A) -next instruction.Condition code settings:2 3 4 Resu It in R- 0 0 Zero.- 0 Bit 0 of register R is a 1.nR and continue toOBit 0 of register R is a 0 and bit positions 1-31of register R contain at least one 1.evsCONVERT BY SUBTRACTION(yVord index alignment)CONVERT BY SUBTRACTION loads the internal A registerwith the contents of register R, clears the internal B register,and sets an internal counter (n) to O. All conversionvalues are considered to be 32-bit positive quantities. Ifthe nth conversion value (the contents of the word locationpointed to by the effective address plus n) is equal to orless than the current contents of the A register, CVS incrementsn by 1, adds the two's complement of the nth conversionvalue to the contents of the A register, stores thesum in the A regi ster, and stores ali n bi t position n of theB register. If the nth conversion value is greater than thecurrent contents of the A register, CVS only increments nby 1. If n is less than 32 after being incremented, thenext conversion value is compared and the process continuesthrough n equal to 31; the remainder in the A registeris loaded into register R, and the converted quantityin the B register is loaded into register Ru1.Affected: (R), (Rul), CC3, CC4(R)-A, O-B, O-nIf (EWL + n) $ (A) then A - (EWL + n) -A,l-B ,n + l-nnIf (EWL + n) > (A) then n + 1-nIf n < 32, repeat; otherwise, (A) - R, (B) - Ru1 andcontinue to the next instruction.Condition code settings:2 3 4 Result in Rul- 0 0 Zero.oBit 0 of register Ru i is a Lo BitOofregisterRu1 is a 0 and bit positions1-31 of register Ru 1 contain at leastone 1.FLOATING-POINT ARITHMETIC INSTRUCTIONSThe floating-point arithmetic instructions are:Instruction f'~amcFloating Add Short~,~ncmon;cFASo- - Sum is correct (less than ~2).Floating Add LongFAL- - Sum is greater than 2 32 _1.Floating Subtract ShortFSS74 Floating-Point Arithmetic Instructions