1. xerox 560 computer system - The UK Mirror Service

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4. INPUT/OUTPUT OPERA TIO NS 142 AGURESExternal DIO Interface 142 1. A Xerox 560 Computer System 9Multiplexor Input/Output Processor (MIOP)Devi ce Controllers 142 2. The Basic Processor 10Rotating Memory Processor (RMP) 143Input/Output Processor (lOP) Fundamentals __ 143 3. Information Boundaries 13Command List 143Operational IOCD 143 4. Main Memory 15Control IOCD 146I/o Operation Phases 148 5. Addressing Logic 18Preparation Phase 148Initiation Phase 148 6. Index Displacement Alignment (Real andFetching Phase 148 Virtual Addressing Modes) 21Execution Phase 149Termination Phase 151 7. Generation of Actual Addresses Indirect,Virtual Addressing 225. OPERATIONAL CONTROL 152 8. Index Displacement Alignment (Real-Extended Addressing) 23Externa I Control Subsystem 152Central ized System Control 152 9. Generation of Effective Virtual AddressControl Console Devices 152 (Indirect Real-Extended Addressing) 24Control Commands 153Operator Control Commands 153 10. Operational States of an Interrupt Level 31Diagnosti c Control Commands 156Maintenance Control Commands 158 1l. Interrupt Priority Chain 34System Control Panel 161Operating Procedures and Information ___ 16412. Typical 28-Word Portion of Memory Stackfor PSS and P LS 1026. SYSTEM CONFIGURATION CONTROL 167 13. Formats of I/o Instructions 128Configuration Control Panel (CCP) 167 14. Bootstrap Loader 155APPENDIXES15.System Control Panel 16216. Chassis Physical Configuration 168A. REFERENC E TABLES 17317. Sample Rows of CCP Switches 168Standard Symbols and Codes 173Standard Character Sets 173Control Codes 173Special Code Properties 173Standard 8-Bit Computer Codes (EBCDIC)___ 174Standard 7-Bit Communication CodesTABLES(ANSCII) 174Standard Symbol-Code Correspondences 175 l. Basic Processor Operating Modes andHexadecimal Arithmetic 179 Address i ng Cases 25Addition Table 179Multiplication Table 179 2. Interrupt Locations 33Table of Powers of SixteenlO 180Table of Powers of Ten16 180 3. Summary of Trap Locations 37Hexadecimal-Decimal Integer ConversionTable 181 4. TCC Setting for Instruction ExceptionHexadecimal-Decimal Fraction Conversion Trap X'4D' 44Table 187Table of Powers of Two 191 5. Registers Changed at Time of a Trap Due toMathematica I Constants 191 an Operand Access 45B. GLOSSARY OF SYMBOLIC TERMS 192 6. ANALYZE Table for Operation Codes 57C. FAULT STATUS REGISTERS 195 7. Floating-Point Number Representation 76iv
Page 1 and 2: Xerox 560 ComputerReference Manual9
Page 6 and 7: 8. Condition Code Settings for Floa
Page 8: • Extensive instruction set that
Page 11 and 12: (also, by a single instruction). Th
Page 13 and 14: MULTIPORT MEMORY SYSTEMThe system h
Page 15 and 16: MemoryUnHMemoryUnitMemoryUnitSystem
Page 18 and 19: MASTER MODEThe master/slave control
Page 20 and 21: Bits1-7DescriptionOperation code. T
Page 22 and 23: PORTS AND MEMORY BUSESA memory unit
Page 24 and 25: Fetch contents of register.yesAdd 1
Page 26 and 27: 8. Real addressing is allowed in ma
Page 28 and 29: Instruction in memory:Instruction i
Page 30 and 31: Instruction in memory:Instruction i
Page 34 and 35: 11-bit page address in the accessed
Page 36 and 37: DesignationFunctionEI External inte
Page 38 and 39: ~ ___basic processor to execute the
Page 40 and 41: 1st Priority 2nd Priority 3rd Prior
Page 42 and 43: TRANSLA TE AND TEST BYTE STRING (TT
Page 44 and 45: Table 3. Summary of Trap Locations
Page 46 and 47: system. If the basic processor is i
Page 48 and 49: 2.CC1 toCC2 CC3 CC4 MeaningNo carry
Page 50 and 51: etry only for hardware errors that
Page 52 and 53: Table 5. Registers Changed at Time
Page 54 and 55:
IIcontinue after interruptll. In th
Page 56 and 57:
the contents of the affected genera
Page 58 and 59:
LCWLOAD COMPLEMENT WORD0/Vord index
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Condition code settings:2 3 4 Resul
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STHSTORE HALFWORD(Halfword index al
Page 64 and 65:
The nonexistent instruction, the pr
Page 66 and 67:
Instruction NameDivide WordMnemonic
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SHSUBTRACT HALFWORD(Halfword index
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MWMULTIPLY WORD0Nord index alignmen
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If the value of the R field is zero
Page 74 and 75:
2 3 4 Result of Comparison- 0 No I-
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ANDAND WORD0Nord index alignment)am
Page 78 and 79:
Bits 0-24 of register 1 are cleared
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to as conversion values. The interm
Page 82 and 83:
Table 7.Floating-Point Number Repre
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If characteristic overflow occurs,
Page 86 and 87:
FMSFLOATING MULTIPLY SHORT(yVord in
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OVERFLOW DETECTIONArithmetic overfl
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DMDECIMAL MULTIPLY(Byte index align
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ExamEle 2, L = 6:Example 1, L = 10:
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In the descriptions of the byte-str
Page 96 and 97:
the destination byte string begins
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••••Contents of register R:
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3.4.5.If the pattern byte is a fiel
Page 102 and 103:
The new contents of the destination
Page 104 and 105:
3. The space count (SPD33-47) is de
Page 106 and 107:
Condition code settings:2 30 0 00 0
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PSS OperationsPLS Operationsinitial
Page 110 and 111:
Depending upon the type of addressi
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Note; If the word count ~ 28, the e
Page 114 and 115:
BIRBRANCH ON INCREMENTING REGISTER(
Page 116 and 117:
BitPosition Designation. Function8
Page 118 and 119:
memory control feature, CC2 and CC4
Page 120 and 121:
Normally, bit positions 15-31 may b
Page 122 and 123:
MEMORY WRITE PROTECTION LOCKSWhen l
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2 3 4 Results in R register- 0o11o
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single-instruction interrupt locati
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READ DIRECT (MODE 9)READ CONFIGURAT
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Table 12. Chassis Type AssignmentsC
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WRITE INTO INTERNAL CONTROL REGISTE
Page 134 and 135:
o 2 3 4 5 6 78 9 10 11 12 13 '4'5 1
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Table 13. Description of I/O Instru
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Table 15. Device Status Byte (Regis
Page 140 and 141:
POLP and POLR INSTRUCTIONSThe R fie
Page 142 and 143:
Status information for an S10 instr
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2 3 4 Meaningoo Processor Interface
Page 146 and 147:
The POLR instruction also resets an
Page 148 and 149:
4. INPUT jOUTPUT OPERATIONSTo accom
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Orders that are executed by a speci
Page 152 and 153:
I/o subchannel (i. e., data transfe
Page 154 and 155:
level within the interrupt system (
Page 156 and 157:
Note: Since the same write key prev
Page 158 and 159:
5. OPERATIONAL CONTROLEXTERNAL CONT
Page 160 and 161:
To prevent inadvertent activation f
Page 162 and 163:
and the IDLE indicator is illuminat
Page 164 and 165:
(P-Mode)GSPECIAL INSTRUCTION SINGLE
Page 166 and 167:
ZCfJlMlSET/CLEAR REPEAT CLOCKING MO
Page 168 and 169:
The controls and indicators of the
Page 170 and 171:
When the CCP/SCSR switch is in the
Page 172 and 173:
BitPosition Status SignificanceTabl
Page 174 and 175:
System Control Panel (SCP)Endbell A
Page 176 and 177:
Table 25. Functions of Processor Cl
Page 179 and 180:
APPENDIX A. REFERENCE TABLESThis ap
Page 181 and 182:
0-9-STANDARD SYMBOL-CODE CORRESPOND
Page 183 and 184:
STANDARD SYMBOL-CODE CORRESPONDENCE
Page 185 and 186:
HEXADECIMAL ARITHMETICADDITION TABL
Page 187 and 188:
HEXADECRAL-DECIMAL INTEGER CONVERSI
Page 189 and 190:
HEXADECIMAL-DECIMAL INTEGER CONVERS
Page 191 and 192:
HEXADECIMAL-DECIMAL INTEGER CONVERS
Page 193 and 194:
HEXADECIMAL·DECIMAL FRACTION CONVE
Page 195 and 196:
HEXADECIMAL-DECIMAL FRACTION CONVER
Page 197 and 198:
TABLE OF POWERS OF TWOMATHEMATICAL
Page 199 and 200:
TermMeaningTermMeaningFZFloating ze
Page 201 and 202:
APPENDIX C.FAULT STATUS REGISTERSTa
Page 203 and 204:
XEROXPublication Revision SheetJANU
Page 205 and 206:
~taplevU:lfJlt:FoldFirst ClassPermi
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