1. xerox 560 computer system - The UK Mirror Service

II, EI) are generated by II ORing" the old CI, II, EI bitswith the contents of bits 37, 38, and 39 of the PSWs aspu II ed from the memory stack.The clearing and arming or disarming the highest priorityinterrupt level currently active is dependent upon thecoding of the CL and AD flags (bit positions 10 and 11,respectively) of the PLS instruction. If the CL flag is a 0 7the interrupt level is not affected. If the CL flag fs-a 1and the AD flag is a Or the interrupt level is set to the disarmedstate. If the CL flag is a 1 and the AD flag is a 1rthe interrupt level is set to the armed state. Note that -ifthe interrupt level is to be modifie~ (CL flag is set to a 1),the instruction maybe delayed unti I the interrupt system isavai lable. -Summary description of CL and AD flags and effect on in-­terrupt level and PDF flag follows:armed state. Note that if the interrupt_level is to bemodified (i. e., the CL flag is a 1), the instruction may bedelayed unti I the interrupt system is avai lab Ie.A summary description of the action on the interrupt leveias a function of the C1 and AD .flag is as follows:Bit Positions10 (CL)oo11 (AD)ooFunctionNo effect upon interrupt levelor PDF flagReset PDF flagClear and disarm interrupt levelClear and arm interrupt levelBit Positions10 (CL)oo11 (AD)ooFunctionNo effect upon interrupt levelor PDF flag.Reset PDF flagClear and disClrm interrupt levelClear and arm interrupt levelIf the initial Word Count within the Status Stack PointerDoubleword is less than 28 cmd not equal to 0, the basicprocessor traps to location X'4D~ (instruction exceptiontrap) without loading-any new status or affecting the parametersof the Status Stack Pointer Doubleword and ther-CC2 bit is set to 1.Affected: If word count ~ 28,(PSWs), CC,Status Stack PointerDoublewordInterrupt System if(1)10=1.Traps: Instruction exception,if word countis less than 28 andnot 0; nonexistentinstruction ifbit 0=1.If the initial Word Count is zero r default PSWs are loaded -from real memory locations 2 and 3 and the other parametersof the Status Stack Pointer Doubleword are not effectiveand no parameters are affected.Portions of the new PSWs (interrupt inhibit group bits andthe Register Block Pointer) may be selected or generated inthe following manner:If the LP flag (bit 8) of the PSL instruction is a 1r the newRegister Block Pointer wi II be as obtained from the defaultPSWs. If the LP flag is a 0, the Register Block Pointer ofthe old PSWs is retained as the Register Block Pointer forthe new PSWs.The CI, II, and EI bits of the old PSWs are "ORed II withthe contents of bit positions 37, 38 r and 39 of the defaultPSWs to generate the CI, II, and EI bits of the new PSWs.Depending upon the coding of the CL and AD flags (bitpositions 10 and 11, respectively) of the PLS instruction,the highest priority interrupt level currently in the activestate may be modified. If the CL flag is a 0, the interruptlevel is not affected. If the CL flag is a 1 and the AD flagis a 0, the interrupt level is cleared and placed into thedisarmed state. If the CL flag is a 1 and the AD flag isa 1, the interrupt level is cleared and placed into the(PSWs) and CCIf word count = 0, (PSWs), ec, and InferruptSystem, if 1(10)=1.ED O_ 3-CC;ED 5-7 -ED 8-MS;-ED 9-MM;ED lO-DM;ED 11-AM;ED 15- 31-FS, FZ, FN;IA;ED 32_ 35-WKED37-39 u CI, II,-EI -CI, II, EI(Note: "u" represents inclusive OR. )[D 56- 59- RP only if (1)8= 1ED 60-RAED 61-MApush-Down Instructions (Privi leged) 105