1. xerox 560 computer system - The UK Mirror Service

DesignationFunctionDesignationFunctionCC Condition code. This generalized 4-bitcode indicates the nature of the results of aninstruction. The significance of the conditioncode bits depends upon the particular instructionjust executed. After an instruction isexecuted, the BRANCH ON CONDITIONSSET (BCS) and BRANCH ON CONDITIONSRESET (BCR) instructions can be used singlyor in combination to test for a particular conditioncode setting. (These instructions aredescribed in Chapter 3, "Execute/BranchInstructions") •FRFSFZIn some operations onlya portion of the conditioncode is involved; thus, the term CC 1refers to the first bit of the condition code,CC2 to the second bit, and CC3 and CC4,respectively, to the third and fourth bits. Anyprogram can change the current value of thecondition code by executing either the LOADCONDITIONS AND FLOATING CONTROLIMMEDIATE (LCFI) or the LOAD CONDI­TIONS AND FLOATING CONTROL (LCF)instruction. Any program can store the currentcondition code by executing the STORECONDITIONS AND FLOATING CONTROL(STCF) instruction. These instructions aredescribed in Chapter 3, ;;Load/~toreInstructions" .Floating round mode control (see FN below).Floating significance mode control (see FNbelow).Floating zero mode control (see FN below).MS Master/slave mode control. The basic processoris in the master mode when this bit andthe mode altered bit (bit 61) both containzero; it is in the slave mode when this bitcontains one. (See MS for a description ofmaster-protected mode.) A master mode ormaster-protected mode program can changethis mode control bit by executing theLOAD PROGRAM STATUS WORDS (LPSD),EXCHANGE PROGRAM STATUS WORDS(XPSD), PUSH STATUS (PSS), or PULL STATUS(PLS) instruction. These privi leged instructionsare described in Chapter 3, "ControlInstructions" •MM Memory map control. The memory map is ineffect when this bit position contains a one.A master mode or master-protected mode programcan change the· memory map control byexecuting an LPSD, XPSD, PSS, or PLSinstruction.DM Decimal mask. The decimal arithmetic trap(see "Trap System", later in this chapter) ispermitted to occur when this bit position containsa one. The conditions that cause adecimal arithmetic trap are described in Chapter3, II Decimal Instructions". The decimaltrap mask can be changed by a master modeor master-protected mode program executingthe LPSD, XPSD, PSS, or PLS instruction.AMArithmetic mask. The fixed-point arithmeticoverflow trap is permitted to occur when thisbit contains one. The instructions that cancause fixed-point overflow are described inthe section "Trap System", later in this chapter.The arithmetic trap mask can be changedby a master mode or master-protected modeprogram executing an LPSD, XPSD, PSS, orPLS instruction.FNFloating normalize mode control. The fourfloating-point mode control bits (FR, FS, FZ,and FN) control the operation of the basicprocessor with respect to invoking the roundoffmode of floating-point calculations,checking floating-point significance, generatingzero results, and normalizing theresults of floating-point additions and subtractions,respectively. (The floating-pointmode controls are described in Chapter 3,"Floating-Point Instructions".) Any programcan change the state of the current floatingpointmode controls by executing either theLCFI or the LCF instruction. Any program canstore the current state of the current floatingpointmode controls by executing the STCFinstruction.IAWKCIIIInstruction address. This 17-bit field containsthe virtual address of the next instruction tobe executed.Write key. This field contains the 4-bit keyused in conjunction with a write lock in thememory write protection feature. A mastermode or master-protected mode program canchange the value of the write key by executingan LPSD, XPSD, PSS, or PLS instruction.Counter interrupt group inhibit (see EI, below).Input/output interrupt group inhibit (see EI,below).Main Memory 29