1. xerox 560 computer system - The UK Mirror Service

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STHSTORE HALFWORD(Halfword index alignment)Example 2, odd R field value:Before executionAfter execution(R)X I 89ABCDEF'X'89ABCDEF'STORE HALFWORD stores the contents of bit positions 16-31of register R into the effective halfword location. If theinformation in register R exceeds halfword data limits, CC2is set to 1; otherwise, CC2 is reset to O.Affected: (EHL), CC2(R)16-31- EHL(E D L) = xxxxxxxxxxxxxxxxSTSSTORE SE LECTNE(Word index alignment)X I 89ABCDEF89ABCDEF'Condition code settings:2 3 4 Information in R- 0 (R)0-16 = all O's or all lis.STW(R)0-16 I all O'S or all l'.s.STORE WORD(Word index alignment)Register Rul contains a 32-bit mask. If R is an even value,STORE SELECTIVE stores the contents of register R into theeffective word location in those bit positions selected bya 1 in corresponding bit positions of register Rul; the effectiveword remains unchanged in those bit positions selectedby a 0 in corresponding bit positions of register Rul.If R is an odd value, STS logically inclusive ORs the contentsof register R with the effective word and stores theresult into the effective word location. The contents ofregister R are not affected.STORE WORD stores the contents of register R into the effectiveword location.Affected: (EWL)Affected: (EWL)If R is even, [(R)n(Rul)] u [EWn(Rul)] -If R is odd, (R) u EW - EWLExample 1, even R field value:EWL(R) -EWLBefore executionAfter executionSTDSTORE DOUBLEWORD(Doubleword index alignment)(R)X'12345678'(Ru 1) = X' FOFOFOFO 'X'12345678'X' FOFOFOFO'EWxxxxxxxxX'lx3x5x7x'STORE DOUBLEWORD stores the contents of register R intothe 32 high-order bit positions of the effective doublewordlocati on and then stores the contents of regi ster Ru 1 intothe 32 low-order bit positions of the effective doublewordlocation.Affected: (E D L)(R)EWBefore executionX'OOFFOOFF'X'12345678'After executionX'OOFFOOFF'C' 12FF56FF I(R) - EDL _ ; (RuH - O 31EDL _ 32 63Example 1, even R field value:Before execution After execution(R) X 1 01234567' X 1 01234567'(Rul) = X'89ABCDEF' X'89ABCDEF '(ED L):::= xxxxxxxxxxxxxxxx X'Q 123456789ABCDEF'STMSTORE MULTIPLE(Word index alignment)/*/ 2B I R I X I I Reference address I10 1 ] 23145 718 9 ]0 11112 13 14'151]6 17 18 19120 21 22 23!24 25 26 27128 29 30 31'STORE MULTIPLE stores the contents of a sequential set ofregisters into a sequential set of word locations. The set oflocations begins with the 10catiol1 pointed to by the effectiveword address of STM, and the set of registers begins with register R. The set of regi sters is treated modu fo 16 (i. e., the56 Load/Store Instructions
next sequential register after register 15 is register 0). Thenumber of registers to be stored is determined by the valueof the condition code immedi ate Iy before execution of STM.(The condition code can be set to the desired value beforeexecution of STM with LCF or LCFI.) An initial valueof 0000 for the condition code causes 16 general registersto be stored.Affected: (EWL) to (EWL +CC-1)(R)-EWL, (R+1)-EWL+1, ... , (R+CC-1)-EWL+CC-1The STM instruction may cause a trap if its operation extendsinto a page of memory that is protected by the accessprotection codes or the write locks. A trap may also occurif the operation extends into a nonexistent memory region.If the effective virtual address of the STM instruction is inthe range 0 through 15, then the registers indicated by theR field of the STM instruction are stored in the general registersrather than main memory. In this case, the resultswill be unpredictable if any of the source registers are alsoused as destination registers.Table 6. ANALYZE Table for Operation CodesX'n' X'OO'+n X'20'+n X'40'+n X'60'+n00 - AI TTBS CBS01 - CI TBS tt MBS02 LCFI ®tt LI -CD -03 - MI - EBS04 CAll SF ANLZ BDR05 CAL2 S CS BIR06 CAL3 LAS XW AWM07 CAL4 - STS EXU08 PLW CYS EOR BCR09 PSW CYA tt OR BCSOA PLM LM@ LS BALOB PSM STM AND INTOC PLS t LRAt SlOt RDtOD psst LMst TIot WDtOE LPSDt@tt WAITt TDyt AIOtOF XPSD t LRPt HIOt MMC tSTCFSTORE CONDITIONS AND FLOATINGCONTROL(Byte index alignment)10 AD SW AH LCF11 CD CW CH CB12 LD LW LH LB13 MSP MTW MTH MTBSTORE CONDITIONS AND FLOATING CONTROL storesthe current condition code and the current value of thefloating round (FR), floating significance (FS), floatingzero (FZ), and floating normalize (FN) mode control bitsof the program status words into the effective byte locationas fo lIows:14 - LYAW - STCF15 STD STW STH STB16 - DWnl-l(A)tt- .. ~ .17 - MW MH UNPK18 SD SW SH DS19 CLM CLR - DA1A LCD LCW LCH DD1B LAD LAW LAH DM- --.. '-.::/PArI( (ffittAffected: (EBL)(PSWs)0_7 -EBL1C FSL FSS - DSA1D FAL FAS - DC1E FDL FDS - DL1F FML FMS - DSTANLZANAL YZEjlNTERPRET INSTRUCTIONSANALYZE(Word index alignment)tPrivileged instructions.tt Decimal value of condition code settings when analyzedinstruction calls for direct addressing. If analyzedinstruction calls for indirect addressing, add 2to the value shown.ANALYZE evaluates the effective word as an instruction.The ANALYZE instruction always sets the condition codesto indicate the addressing type of the analyzed instruction(see condition code settings and Table 6). Except whenthe analyzed instruction is an immediate operand instruction,an effective virtual address for the analyzedinstruction is also calculated and loaded into register R.Analyze/Interpret Instructions 57
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Xerox 560 ComputerReference Manual9
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4. INPUT/OUTPUT OPERA TIO NS 142 AG
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1. XEROX 560 COMPUTER SYSTEMINTRODU
Page 10 and 11:
Many operations are performed in fl
Page 12 and 13: Rapid Context Switching. When respo
Page 14 and 15: 2. SYSTEM ORGANIZATIONThe elements
Page 16: FAST MEMORYARITHMETIC AND CONTROL U
Page 19 and 20: INFORMATION BOUNDARIESBasic process
Page 21 and 22: (Maximumof eight)Core Core Core Cor
Page 23 and 24: 3. Diagnostic logic. Each memory dr
Page 25 and 26: eference address field of the instr
Page 27 and 28: Instruction in memory:Instruction i
Page 29 and 30: Real-extended addressing is specifi
Page 31: Table 1. Basic Processor Operating
Page 35 and 36: DesignationFunctionDesignationFunct
Page 37 and 38: InterruptStateDisarmedArmed[$Waitin
Page 39 and 40: AddressTable 2. Interrupt Locations
Page 41 and 42: is assumed to contain an XPSD or a
Page 43 and 44: Table 3. Summary of Trap LocationsL
Page 45 and 46: TRAP MASKSThe programmer may mask t
Page 47 and 48: PUSH-DOWN STACK LIMIT TRAPPush-down
Page 49 and 50: Instruction Name Mnemonic FaultDeci
Page 51 and 52: subroutine. However, with certain c
Page 53 and 54: 3. INSTRUCTION REPERTOIREThis chapt
Page 55 and 56: CC1 is unchanged by the instruction
Page 57 and 58: Condition code settings:2 3 4 Resul
Page 59 and 60: Example 2, odd R field value:Before
Page 61: significance (FS), floating zero (F
Page 65 and 66: R 1 R2 R3 MeaningoThe effective vir
Page 69 and 70: MIMULTIPLY IMMEDIATE(Immediate oper
Page 71 and 72: original contents of register R, re
Page 73 and 74: Instruction NameCompare HalfwordMne
Page 77 and 78: 2 3 4 Result of ShiftCircular Shift
Page 79 and 80: 4. At the completion of the left sh
Page 81 and 82: Instruction NameFloating Subtract L
Page 83 and 84: The following table shows the possi
Page 85 and 86: Table 8.Condition Code Settings for
Page 87 and 88: PACKED DECIMAL NUMBERSAll decimal a
Page 89 and 90: DSTDECIMAL STORE(Byte index alignme
Page 91 and 92: If no indirect addressing or indexi
Page 93 and 94: Instruction NameMnemonicDesignation
Page 95 and 96: Both byte strings are C bytes in le
Page 97 and 98: of the destination byte that caused
Page 99 and 100: again present, unti I a positive or
Page 101 and 102: The new contents of register 7 are:
Page 103 and 104: traps to location X'42 1 as a resul
Page 105 and 106: If there is sufficient space in the
Page 107 and 108: If CC1, or CC3, or both CC1 and CC3
Page 109 and 110: appropriate memory stack locations
Page 111 and 112: II, EI) are generated by II ORing"
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In the real extended addressing mod
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CAll INSTRUCTIONSEach ofthe four CA
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The XPSD instruction' is used for t
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If (I)1O = 0, trap or interrupt ins
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For either memory map format and ei
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initial value plus the initial valu
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Table 9. Status Word 0Field Bits Co
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READ INTERRUPT INHIBITSThe followin
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Table 11.Read Direct Mode 9 Status
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SET ALARM INDICATORThe following co
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INPUT jOUTPUT INSTRUCTIONSThe I/o i
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Table 13.Description of I/o Instruc
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Table 15.Device Status Byte (Regist
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Table 16. Operational Status Byte (
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Table 19.Status Response Bits for A
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If CC4 = 0, the MIOP is in a normal
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2 3 4 Meaningo 0 I/o address not re
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The functions of bits within the DC
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4. Each unit-record controller (int
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Interrupt at Channel End (Bit Posit
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Transfer in Channel. A control lOCO
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Otherwise, the first word of the ne
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Depending upon the characteristics
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change the rate on the primary cons
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Location(hex) (dec)20 3221 3322 342
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Table 22.Diagnostic Control (P-Mode
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at its normal rate (e. g., fixed du
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SET LOW CLOCK MARGINSThis command c
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BP STATUS AND NO.Th i s group of i
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Input5MPri ntout5MFunctionStore X 1
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6. SYSTEM CONFIGURATION CONTROLPool
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Table 25. Functions of Processor Cl
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Table 26. Functions of Memory Unit
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STANDARD 8-BIT COMPUTER CODES (EBCD
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STANDARD SYMBOL-CODE CORRESPONDENCE
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STANDARD SYMBOL-CODE CORRESPONDENCE
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TABLE OF POWERS OF SIXTEEN II162564
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL FRACTION CONVER
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HEXADECIMAL-DECIMAL FRACTION CONVER
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APPENDIX B.GLOSSARY OF SYMBOLIC TER
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TermMeaningTermMeaningWKxWrite key
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Table C-2. Memory Unit Status Regis
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Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
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